1#[doc = "Register `spi_bcc` reader"]
2pub type R = crate::R<SPI_BCC_SPEC>;
3#[doc = "Register `spi_bcc` writer"]
4pub type W = crate::W<SPI_BCC_SPEC>;
5#[doc = "Field `stc` reader - Master Single Mode Transmit Counter"]
6pub type STC_R = crate::FieldReader<u32>;
7#[doc = "Field `stc` writer - Master Single Mode Transmit Counter"]
8pub type STC_W<'a, REG> = crate::FieldWriter<'a, REG, 24, u32>;
9#[doc = "Field `dbc` reader - Master Dummy Burst Counter"]
10pub type DBC_R = crate::FieldReader;
11#[doc = "Field `dbc` writer - Master Dummy Burst Counter"]
12pub type DBC_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `drm` reader - Master Dual Mode RX Enable"]
14pub type DRM_R = crate::BitReader<DRM_A>;
15#[doc = "Master Dual Mode RX Enable\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17pub enum DRM_A {
18 #[doc = "0: `0`"]
19 SINGLE = 0,
20 #[doc = "1: `1`"]
21 DUAL = 1,
22}
23impl From<DRM_A> for bool {
24 #[inline(always)]
25 fn from(variant: DRM_A) -> Self {
26 variant as u8 != 0
27 }
28}
29impl DRM_R {
30 #[doc = "Get enumerated values variant"]
31 #[inline(always)]
32 pub const fn variant(&self) -> DRM_A {
33 match self.bits {
34 false => DRM_A::SINGLE,
35 true => DRM_A::DUAL,
36 }
37 }
38 #[doc = "`0`"]
39 #[inline(always)]
40 pub fn is_single(&self) -> bool {
41 *self == DRM_A::SINGLE
42 }
43 #[doc = "`1`"]
44 #[inline(always)]
45 pub fn is_dual(&self) -> bool {
46 *self == DRM_A::DUAL
47 }
48}
49#[doc = "Field `drm` writer - Master Dual Mode RX Enable"]
50pub type DRM_W<'a, REG> = crate::BitWriter<'a, REG, DRM_A>;
51impl<'a, REG> DRM_W<'a, REG>
52where
53 REG: crate::Writable + crate::RegisterSpec,
54{
55 #[doc = "`0`"]
56 #[inline(always)]
57 pub fn single(self) -> &'a mut crate::W<REG> {
58 self.variant(DRM_A::SINGLE)
59 }
60 #[doc = "`1`"]
61 #[inline(always)]
62 pub fn dual(self) -> &'a mut crate::W<REG> {
63 self.variant(DRM_A::DUAL)
64 }
65}
66#[doc = "Field `quad_en` reader - Quad Mode Enable"]
67pub type QUAD_EN_R = crate::BitReader<QUAD_EN_A>;
68#[doc = "Quad Mode Enable\n\nValue on reset: 0"]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum QUAD_EN_A {
71 #[doc = "0: `0`"]
72 DISABLE = 0,
73 #[doc = "1: `1`"]
74 ENABLE = 1,
75}
76impl From<QUAD_EN_A> for bool {
77 #[inline(always)]
78 fn from(variant: QUAD_EN_A) -> Self {
79 variant as u8 != 0
80 }
81}
82impl QUAD_EN_R {
83 #[doc = "Get enumerated values variant"]
84 #[inline(always)]
85 pub const fn variant(&self) -> QUAD_EN_A {
86 match self.bits {
87 false => QUAD_EN_A::DISABLE,
88 true => QUAD_EN_A::ENABLE,
89 }
90 }
91 #[doc = "`0`"]
92 #[inline(always)]
93 pub fn is_disable(&self) -> bool {
94 *self == QUAD_EN_A::DISABLE
95 }
96 #[doc = "`1`"]
97 #[inline(always)]
98 pub fn is_enable(&self) -> bool {
99 *self == QUAD_EN_A::ENABLE
100 }
101}
102#[doc = "Field `quad_en` writer - Quad Mode Enable"]
103pub type QUAD_EN_W<'a, REG> = crate::BitWriter<'a, REG, QUAD_EN_A>;
104impl<'a, REG> QUAD_EN_W<'a, REG>
105where
106 REG: crate::Writable + crate::RegisterSpec,
107{
108 #[doc = "`0`"]
109 #[inline(always)]
110 pub fn disable(self) -> &'a mut crate::W<REG> {
111 self.variant(QUAD_EN_A::DISABLE)
112 }
113 #[doc = "`1`"]
114 #[inline(always)]
115 pub fn enable(self) -> &'a mut crate::W<REG> {
116 self.variant(QUAD_EN_A::ENABLE)
117 }
118}
119impl R {
120 #[doc = "Bits 0:23 - Master Single Mode Transmit Counter"]
121 #[inline(always)]
122 pub fn stc(&self) -> STC_R {
123 STC_R::new(self.bits & 0x00ff_ffff)
124 }
125 #[doc = "Bits 24:27 - Master Dummy Burst Counter"]
126 #[inline(always)]
127 pub fn dbc(&self) -> DBC_R {
128 DBC_R::new(((self.bits >> 24) & 0x0f) as u8)
129 }
130 #[doc = "Bit 28 - Master Dual Mode RX Enable"]
131 #[inline(always)]
132 pub fn drm(&self) -> DRM_R {
133 DRM_R::new(((self.bits >> 28) & 1) != 0)
134 }
135 #[doc = "Bit 29 - Quad Mode Enable"]
136 #[inline(always)]
137 pub fn quad_en(&self) -> QUAD_EN_R {
138 QUAD_EN_R::new(((self.bits >> 29) & 1) != 0)
139 }
140}
141impl W {
142 #[doc = "Bits 0:23 - Master Single Mode Transmit Counter"]
143 #[inline(always)]
144 #[must_use]
145 pub fn stc(&mut self) -> STC_W<SPI_BCC_SPEC> {
146 STC_W::new(self, 0)
147 }
148 #[doc = "Bits 24:27 - Master Dummy Burst Counter"]
149 #[inline(always)]
150 #[must_use]
151 pub fn dbc(&mut self) -> DBC_W<SPI_BCC_SPEC> {
152 DBC_W::new(self, 24)
153 }
154 #[doc = "Bit 28 - Master Dual Mode RX Enable"]
155 #[inline(always)]
156 #[must_use]
157 pub fn drm(&mut self) -> DRM_W<SPI_BCC_SPEC> {
158 DRM_W::new(self, 28)
159 }
160 #[doc = "Bit 29 - Quad Mode Enable"]
161 #[inline(always)]
162 #[must_use]
163 pub fn quad_en(&mut self) -> QUAD_EN_W<SPI_BCC_SPEC> {
164 QUAD_EN_W::new(self, 29)
165 }
166 #[doc = r" Writes raw bits to the register."]
167 #[doc = r""]
168 #[doc = r" # Safety"]
169 #[doc = r""]
170 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
171 #[inline(always)]
172 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
173 self.bits = bits;
174 self
175 }
176}
177#[doc = "SPI Master Burst Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_bcc::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_bcc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
178pub struct SPI_BCC_SPEC;
179impl crate::RegisterSpec for SPI_BCC_SPEC {
180 type Ux = u32;
181}
182#[doc = "`read()` method returns [`spi_bcc::R`](R) reader structure"]
183impl crate::Readable for SPI_BCC_SPEC {}
184#[doc = "`write(|w| ..)` method takes [`spi_bcc::W`](W) writer structure"]
185impl crate::Writable for SPI_BCC_SPEC {
186 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
187 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
188}
189#[doc = "`reset()` method sets spi_bcc to value 0"]
190impl crate::Resettable for SPI_BCC_SPEC {
191 const RESET_VALUE: Self::Ux = 0;
192}