d1_pac/spi0/
spi_batc.rs

1#[doc = "Register `spi_batc` reader"]
2pub type R = crate::R<SPI_BATC_SPEC>;
3#[doc = "Register `spi_batc` writer"]
4pub type W = crate::W<SPI_BATC_SPEC>;
5#[doc = "Field `wms` reader - Work Mode Select"]
6pub type WMS_R = crate::FieldReader<WMS_A>;
7#[doc = "Work Mode Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum WMS_A {
11    #[doc = "0: `0`"]
12    BYTE_ALIGNED = 0,
13    #[doc = "2: `10`"]
14    BIT_ALIGNED_3WIRE = 2,
15    #[doc = "3: `11`"]
16    BIT_ALIGNED_STANDARD = 3,
17}
18impl From<WMS_A> for u8 {
19    #[inline(always)]
20    fn from(variant: WMS_A) -> Self {
21        variant as _
22    }
23}
24impl crate::FieldSpec for WMS_A {
25    type Ux = u8;
26}
27impl WMS_R {
28    #[doc = "Get enumerated values variant"]
29    #[inline(always)]
30    pub const fn variant(&self) -> WMS_A {
31        match self.bits {
32            0 => WMS_A::BYTE_ALIGNED,
33            2 => WMS_A::BIT_ALIGNED_3WIRE,
34            3 => WMS_A::BIT_ALIGNED_STANDARD,
35            _ => unreachable!(),
36        }
37    }
38    #[doc = "`0`"]
39    #[inline(always)]
40    pub fn is_byte_aligned(&self) -> bool {
41        *self == WMS_A::BYTE_ALIGNED
42    }
43    #[doc = "`10`"]
44    #[inline(always)]
45    pub fn is_bit_aligned_3wire(&self) -> bool {
46        *self == WMS_A::BIT_ALIGNED_3WIRE
47    }
48    #[doc = "`11`"]
49    #[inline(always)]
50    pub fn is_bit_aligned_standard(&self) -> bool {
51        *self == WMS_A::BIT_ALIGNED_STANDARD
52    }
53}
54#[doc = "Field `wms` writer - Work Mode Select"]
55pub type WMS_W<'a, REG> = crate::FieldWriter<'a, REG, 2, WMS_A>;
56impl<'a, REG> WMS_W<'a, REG>
57where
58    REG: crate::Writable + crate::RegisterSpec,
59    REG::Ux: From<u8>,
60{
61    #[doc = "`0`"]
62    #[inline(always)]
63    pub fn byte_aligned(self) -> &'a mut crate::W<REG> {
64        self.variant(WMS_A::BYTE_ALIGNED)
65    }
66    #[doc = "`10`"]
67    #[inline(always)]
68    pub fn bit_aligned_3wire(self) -> &'a mut crate::W<REG> {
69        self.variant(WMS_A::BIT_ALIGNED_3WIRE)
70    }
71    #[doc = "`11`"]
72    #[inline(always)]
73    pub fn bit_aligned_standard(self) -> &'a mut crate::W<REG> {
74        self.variant(WMS_A::BIT_ALIGNED_STANDARD)
75    }
76}
77#[doc = "Field `ss_sel` reader - SPI Chip Select"]
78pub type SS_SEL_R = crate::FieldReader<SS_SEL_A>;
79#[doc = "SPI Chip Select\n\nValue on reset: 0"]
80#[derive(Clone, Copy, Debug, PartialEq, Eq)]
81#[repr(u8)]
82pub enum SS_SEL_A {
83    #[doc = "0: `0`"]
84    SS0 = 0,
85    #[doc = "1: `1`"]
86    SS1 = 1,
87    #[doc = "2: `10`"]
88    SS2 = 2,
89    #[doc = "3: `11`"]
90    SS3 = 3,
91}
92impl From<SS_SEL_A> for u8 {
93    #[inline(always)]
94    fn from(variant: SS_SEL_A) -> Self {
95        variant as _
96    }
97}
98impl crate::FieldSpec for SS_SEL_A {
99    type Ux = u8;
100}
101impl SS_SEL_R {
102    #[doc = "Get enumerated values variant"]
103    #[inline(always)]
104    pub const fn variant(&self) -> SS_SEL_A {
105        match self.bits {
106            0 => SS_SEL_A::SS0,
107            1 => SS_SEL_A::SS1,
108            2 => SS_SEL_A::SS2,
109            3 => SS_SEL_A::SS3,
110            _ => unreachable!(),
111        }
112    }
113    #[doc = "`0`"]
114    #[inline(always)]
115    pub fn is_ss0(&self) -> bool {
116        *self == SS_SEL_A::SS0
117    }
118    #[doc = "`1`"]
119    #[inline(always)]
120    pub fn is_ss1(&self) -> bool {
121        *self == SS_SEL_A::SS1
122    }
123    #[doc = "`10`"]
124    #[inline(always)]
125    pub fn is_ss2(&self) -> bool {
126        *self == SS_SEL_A::SS2
127    }
128    #[doc = "`11`"]
129    #[inline(always)]
130    pub fn is_ss3(&self) -> bool {
131        *self == SS_SEL_A::SS3
132    }
133}
134#[doc = "Field `ss_sel` writer - SPI Chip Select"]
135pub type SS_SEL_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, SS_SEL_A>;
136impl<'a, REG> SS_SEL_W<'a, REG>
137where
138    REG: crate::Writable + crate::RegisterSpec,
139    REG::Ux: From<u8>,
140{
141    #[doc = "`0`"]
142    #[inline(always)]
143    pub fn ss0(self) -> &'a mut crate::W<REG> {
144        self.variant(SS_SEL_A::SS0)
145    }
146    #[doc = "`1`"]
147    #[inline(always)]
148    pub fn ss1(self) -> &'a mut crate::W<REG> {
149        self.variant(SS_SEL_A::SS1)
150    }
151    #[doc = "`10`"]
152    #[inline(always)]
153    pub fn ss2(self) -> &'a mut crate::W<REG> {
154        self.variant(SS_SEL_A::SS2)
155    }
156    #[doc = "`11`"]
157    #[inline(always)]
158    pub fn ss3(self) -> &'a mut crate::W<REG> {
159        self.variant(SS_SEL_A::SS3)
160    }
161}
162#[doc = "Field `spol` reader - SPI Chip Select Signal Polarity Control"]
163pub type SPOL_R = crate::BitReader<SPOL_A>;
164#[doc = "SPI Chip Select Signal Polarity Control\n\nValue on reset: 0"]
165#[derive(Clone, Copy, Debug, PartialEq, Eq)]
166pub enum SPOL_A {
167    #[doc = "0: `0`"]
168    HIGH = 0,
169    #[doc = "1: `1`"]
170    LOW = 1,
171}
172impl From<SPOL_A> for bool {
173    #[inline(always)]
174    fn from(variant: SPOL_A) -> Self {
175        variant as u8 != 0
176    }
177}
178impl SPOL_R {
179    #[doc = "Get enumerated values variant"]
180    #[inline(always)]
181    pub const fn variant(&self) -> SPOL_A {
182        match self.bits {
183            false => SPOL_A::HIGH,
184            true => SPOL_A::LOW,
185        }
186    }
187    #[doc = "`0`"]
188    #[inline(always)]
189    pub fn is_high(&self) -> bool {
190        *self == SPOL_A::HIGH
191    }
192    #[doc = "`1`"]
193    #[inline(always)]
194    pub fn is_low(&self) -> bool {
195        *self == SPOL_A::LOW
196    }
197}
198#[doc = "Field `spol` writer - SPI Chip Select Signal Polarity Control"]
199pub type SPOL_W<'a, REG> = crate::BitWriter<'a, REG, SPOL_A>;
200impl<'a, REG> SPOL_W<'a, REG>
201where
202    REG: crate::Writable + crate::RegisterSpec,
203{
204    #[doc = "`0`"]
205    #[inline(always)]
206    pub fn high(self) -> &'a mut crate::W<REG> {
207        self.variant(SPOL_A::HIGH)
208    }
209    #[doc = "`1`"]
210    #[inline(always)]
211    pub fn low(self) -> &'a mut crate::W<REG> {
212        self.variant(SPOL_A::LOW)
213    }
214}
215#[doc = "Field `ss_owner` reader - SS Output Owner Select"]
216pub type SS_OWNER_R = crate::BitReader<SS_OWNER_A>;
217#[doc = "SS Output Owner Select\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219pub enum SS_OWNER_A {
220    #[doc = "0: `0`"]
221    SPI_CONTROLLER = 0,
222    #[doc = "1: `1`"]
223    SOFTWARE = 1,
224}
225impl From<SS_OWNER_A> for bool {
226    #[inline(always)]
227    fn from(variant: SS_OWNER_A) -> Self {
228        variant as u8 != 0
229    }
230}
231impl SS_OWNER_R {
232    #[doc = "Get enumerated values variant"]
233    #[inline(always)]
234    pub const fn variant(&self) -> SS_OWNER_A {
235        match self.bits {
236            false => SS_OWNER_A::SPI_CONTROLLER,
237            true => SS_OWNER_A::SOFTWARE,
238        }
239    }
240    #[doc = "`0`"]
241    #[inline(always)]
242    pub fn is_spi_controller(&self) -> bool {
243        *self == SS_OWNER_A::SPI_CONTROLLER
244    }
245    #[doc = "`1`"]
246    #[inline(always)]
247    pub fn is_software(&self) -> bool {
248        *self == SS_OWNER_A::SOFTWARE
249    }
250}
251#[doc = "Field `ss_owner` writer - SS Output Owner Select"]
252pub type SS_OWNER_W<'a, REG> = crate::BitWriter<'a, REG, SS_OWNER_A>;
253impl<'a, REG> SS_OWNER_W<'a, REG>
254where
255    REG: crate::Writable + crate::RegisterSpec,
256{
257    #[doc = "`0`"]
258    #[inline(always)]
259    pub fn spi_controller(self) -> &'a mut crate::W<REG> {
260        self.variant(SS_OWNER_A::SPI_CONTROLLER)
261    }
262    #[doc = "`1`"]
263    #[inline(always)]
264    pub fn software(self) -> &'a mut crate::W<REG> {
265        self.variant(SS_OWNER_A::SOFTWARE)
266    }
267}
268#[doc = "Field `ss_level` reader - "]
269pub type SS_LEVEL_R = crate::BitReader<SS_LEVEL_A>;
270#[doc = "\n\nValue on reset: 0"]
271#[derive(Clone, Copy, Debug, PartialEq, Eq)]
272pub enum SS_LEVEL_A {
273    #[doc = "0: `0`"]
274    LOW = 0,
275    #[doc = "1: `1`"]
276    HIGH = 1,
277}
278impl From<SS_LEVEL_A> for bool {
279    #[inline(always)]
280    fn from(variant: SS_LEVEL_A) -> Self {
281        variant as u8 != 0
282    }
283}
284impl SS_LEVEL_R {
285    #[doc = "Get enumerated values variant"]
286    #[inline(always)]
287    pub const fn variant(&self) -> SS_LEVEL_A {
288        match self.bits {
289            false => SS_LEVEL_A::LOW,
290            true => SS_LEVEL_A::HIGH,
291        }
292    }
293    #[doc = "`0`"]
294    #[inline(always)]
295    pub fn is_low(&self) -> bool {
296        *self == SS_LEVEL_A::LOW
297    }
298    #[doc = "`1`"]
299    #[inline(always)]
300    pub fn is_high(&self) -> bool {
301        *self == SS_LEVEL_A::HIGH
302    }
303}
304#[doc = "Field `ss_level` writer - "]
305pub type SS_LEVEL_W<'a, REG> = crate::BitWriter<'a, REG, SS_LEVEL_A>;
306impl<'a, REG> SS_LEVEL_W<'a, REG>
307where
308    REG: crate::Writable + crate::RegisterSpec,
309{
310    #[doc = "`0`"]
311    #[inline(always)]
312    pub fn low(self) -> &'a mut crate::W<REG> {
313        self.variant(SS_LEVEL_A::LOW)
314    }
315    #[doc = "`1`"]
316    #[inline(always)]
317    pub fn high(self) -> &'a mut crate::W<REG> {
318        self.variant(SS_LEVEL_A::HIGH)
319    }
320}
321#[doc = "Field `tx_frm_len` reader - Configure the length of serial data frame of TX"]
322pub type TX_FRM_LEN_R = crate::FieldReader;
323#[doc = "Field `tx_frm_len` writer - Configure the length of serial data frame of TX"]
324pub type TX_FRM_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
325#[doc = "Field `rx_frm_len` reader - Configure the length of serial data frame of RX"]
326pub type RX_FRM_LEN_R = crate::FieldReader;
327#[doc = "Field `rx_frm_len` writer - Configure the length of serial data frame of RX"]
328pub type RX_FRM_LEN_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
329#[doc = "Field `tbc_int_en` reader - Transfer Bits Completed Interrupt Enable"]
330pub type TBC_INT_EN_R = crate::BitReader<TBC_INT_EN_A>;
331#[doc = "Transfer Bits Completed Interrupt Enable\n\nValue on reset: 0"]
332#[derive(Clone, Copy, Debug, PartialEq, Eq)]
333pub enum TBC_INT_EN_A {
334    #[doc = "0: `0`"]
335    DISABLE = 0,
336    #[doc = "1: `1`"]
337    ENABLE = 1,
338}
339impl From<TBC_INT_EN_A> for bool {
340    #[inline(always)]
341    fn from(variant: TBC_INT_EN_A) -> Self {
342        variant as u8 != 0
343    }
344}
345impl TBC_INT_EN_R {
346    #[doc = "Get enumerated values variant"]
347    #[inline(always)]
348    pub const fn variant(&self) -> TBC_INT_EN_A {
349        match self.bits {
350            false => TBC_INT_EN_A::DISABLE,
351            true => TBC_INT_EN_A::ENABLE,
352        }
353    }
354    #[doc = "`0`"]
355    #[inline(always)]
356    pub fn is_disable(&self) -> bool {
357        *self == TBC_INT_EN_A::DISABLE
358    }
359    #[doc = "`1`"]
360    #[inline(always)]
361    pub fn is_enable(&self) -> bool {
362        *self == TBC_INT_EN_A::ENABLE
363    }
364}
365#[doc = "Field `tbc_int_en` writer - Transfer Bits Completed Interrupt Enable"]
366pub type TBC_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, TBC_INT_EN_A>;
367impl<'a, REG> TBC_INT_EN_W<'a, REG>
368where
369    REG: crate::Writable + crate::RegisterSpec,
370{
371    #[doc = "`0`"]
372    #[inline(always)]
373    pub fn disable(self) -> &'a mut crate::W<REG> {
374        self.variant(TBC_INT_EN_A::DISABLE)
375    }
376    #[doc = "`1`"]
377    #[inline(always)]
378    pub fn enable(self) -> &'a mut crate::W<REG> {
379        self.variant(TBC_INT_EN_A::ENABLE)
380    }
381}
382#[doc = "Field `tbc` reader - Transfer Bits Completed"]
383pub type TBC_R = crate::BitReader<TBC_A>;
384#[doc = "Transfer Bits Completed\n\nValue on reset: 0"]
385#[derive(Clone, Copy, Debug, PartialEq, Eq)]
386pub enum TBC_A {
387    #[doc = "0: `0`"]
388    BUSY = 0,
389    #[doc = "1: `1`"]
390    COMPLETED = 1,
391}
392impl From<TBC_A> for bool {
393    #[inline(always)]
394    fn from(variant: TBC_A) -> Self {
395        variant as u8 != 0
396    }
397}
398impl TBC_R {
399    #[doc = "Get enumerated values variant"]
400    #[inline(always)]
401    pub const fn variant(&self) -> TBC_A {
402        match self.bits {
403            false => TBC_A::BUSY,
404            true => TBC_A::COMPLETED,
405        }
406    }
407    #[doc = "`0`"]
408    #[inline(always)]
409    pub fn is_busy(&self) -> bool {
410        *self == TBC_A::BUSY
411    }
412    #[doc = "`1`"]
413    #[inline(always)]
414    pub fn is_completed(&self) -> bool {
415        *self == TBC_A::COMPLETED
416    }
417}
418#[doc = "Field `tbc` writer - Transfer Bits Completed"]
419pub type TBC_W<'a, REG> = crate::BitWriter<'a, REG, TBC_A>;
420impl<'a, REG> TBC_W<'a, REG>
421where
422    REG: crate::Writable + crate::RegisterSpec,
423{
424    #[doc = "`0`"]
425    #[inline(always)]
426    pub fn busy(self) -> &'a mut crate::W<REG> {
427        self.variant(TBC_A::BUSY)
428    }
429    #[doc = "`1`"]
430    #[inline(always)]
431    pub fn completed(self) -> &'a mut crate::W<REG> {
432        self.variant(TBC_A::COMPLETED)
433    }
434}
435#[doc = "Field `msms` reader - Master Sample Standard"]
436pub type MSMS_R = crate::BitReader<MSMS_A>;
437#[doc = "Master Sample Standard\n\nValue on reset: 0"]
438#[derive(Clone, Copy, Debug, PartialEq, Eq)]
439pub enum MSMS_A {
440    #[doc = "0: `0`"]
441    DELAY = 0,
442    #[doc = "1: `1`"]
443    STANDARD = 1,
444}
445impl From<MSMS_A> for bool {
446    #[inline(always)]
447    fn from(variant: MSMS_A) -> Self {
448        variant as u8 != 0
449    }
450}
451impl MSMS_R {
452    #[doc = "Get enumerated values variant"]
453    #[inline(always)]
454    pub const fn variant(&self) -> MSMS_A {
455        match self.bits {
456            false => MSMS_A::DELAY,
457            true => MSMS_A::STANDARD,
458        }
459    }
460    #[doc = "`0`"]
461    #[inline(always)]
462    pub fn is_delay(&self) -> bool {
463        *self == MSMS_A::DELAY
464    }
465    #[doc = "`1`"]
466    #[inline(always)]
467    pub fn is_standard(&self) -> bool {
468        *self == MSMS_A::STANDARD
469    }
470}
471#[doc = "Field `msms` writer - Master Sample Standard"]
472pub type MSMS_W<'a, REG> = crate::BitWriter<'a, REG, MSMS_A>;
473impl<'a, REG> MSMS_W<'a, REG>
474where
475    REG: crate::Writable + crate::RegisterSpec,
476{
477    #[doc = "`0`"]
478    #[inline(always)]
479    pub fn delay(self) -> &'a mut crate::W<REG> {
480        self.variant(MSMS_A::DELAY)
481    }
482    #[doc = "`1`"]
483    #[inline(always)]
484    pub fn standard(self) -> &'a mut crate::W<REG> {
485        self.variant(MSMS_A::STANDARD)
486    }
487}
488#[doc = "Field `tce` reader - Transfer Control Enable"]
489pub type TCE_R = crate::BitReader<TCE_A>;
490#[doc = "Transfer Control Enable\n\nValue on reset: 0"]
491#[derive(Clone, Copy, Debug, PartialEq, Eq)]
492pub enum TCE_A {
493    #[doc = "0: `0`"]
494    IDLE = 0,
495    #[doc = "1: `1`"]
496    INIT = 1,
497}
498impl From<TCE_A> for bool {
499    #[inline(always)]
500    fn from(variant: TCE_A) -> Self {
501        variant as u8 != 0
502    }
503}
504impl TCE_R {
505    #[doc = "Get enumerated values variant"]
506    #[inline(always)]
507    pub const fn variant(&self) -> TCE_A {
508        match self.bits {
509            false => TCE_A::IDLE,
510            true => TCE_A::INIT,
511        }
512    }
513    #[doc = "`0`"]
514    #[inline(always)]
515    pub fn is_idle(&self) -> bool {
516        *self == TCE_A::IDLE
517    }
518    #[doc = "`1`"]
519    #[inline(always)]
520    pub fn is_init(&self) -> bool {
521        *self == TCE_A::INIT
522    }
523}
524#[doc = "Field `tce` writer - Transfer Control Enable"]
525pub type TCE_W<'a, REG> = crate::BitWriter<'a, REG, TCE_A>;
526impl<'a, REG> TCE_W<'a, REG>
527where
528    REG: crate::Writable + crate::RegisterSpec,
529{
530    #[doc = "`0`"]
531    #[inline(always)]
532    pub fn idle(self) -> &'a mut crate::W<REG> {
533        self.variant(TCE_A::IDLE)
534    }
535    #[doc = "`1`"]
536    #[inline(always)]
537    pub fn init(self) -> &'a mut crate::W<REG> {
538        self.variant(TCE_A::INIT)
539    }
540}
541impl R {
542    #[doc = "Bits 0:1 - Work Mode Select"]
543    #[inline(always)]
544    pub fn wms(&self) -> WMS_R {
545        WMS_R::new((self.bits & 3) as u8)
546    }
547    #[doc = "Bits 2:3 - SPI Chip Select"]
548    #[inline(always)]
549    pub fn ss_sel(&self) -> SS_SEL_R {
550        SS_SEL_R::new(((self.bits >> 2) & 3) as u8)
551    }
552    #[doc = "Bit 5 - SPI Chip Select Signal Polarity Control"]
553    #[inline(always)]
554    pub fn spol(&self) -> SPOL_R {
555        SPOL_R::new(((self.bits >> 5) & 1) != 0)
556    }
557    #[doc = "Bit 6 - SS Output Owner Select"]
558    #[inline(always)]
559    pub fn ss_owner(&self) -> SS_OWNER_R {
560        SS_OWNER_R::new(((self.bits >> 6) & 1) != 0)
561    }
562    #[doc = "Bit 7"]
563    #[inline(always)]
564    pub fn ss_level(&self) -> SS_LEVEL_R {
565        SS_LEVEL_R::new(((self.bits >> 7) & 1) != 0)
566    }
567    #[doc = "Bits 8:13 - Configure the length of serial data frame of TX"]
568    #[inline(always)]
569    pub fn tx_frm_len(&self) -> TX_FRM_LEN_R {
570        TX_FRM_LEN_R::new(((self.bits >> 8) & 0x3f) as u8)
571    }
572    #[doc = "Bits 16:21 - Configure the length of serial data frame of RX"]
573    #[inline(always)]
574    pub fn rx_frm_len(&self) -> RX_FRM_LEN_R {
575        RX_FRM_LEN_R::new(((self.bits >> 16) & 0x3f) as u8)
576    }
577    #[doc = "Bit 24 - Transfer Bits Completed Interrupt Enable"]
578    #[inline(always)]
579    pub fn tbc_int_en(&self) -> TBC_INT_EN_R {
580        TBC_INT_EN_R::new(((self.bits >> 24) & 1) != 0)
581    }
582    #[doc = "Bit 25 - Transfer Bits Completed"]
583    #[inline(always)]
584    pub fn tbc(&self) -> TBC_R {
585        TBC_R::new(((self.bits >> 25) & 1) != 0)
586    }
587    #[doc = "Bit 30 - Master Sample Standard"]
588    #[inline(always)]
589    pub fn msms(&self) -> MSMS_R {
590        MSMS_R::new(((self.bits >> 30) & 1) != 0)
591    }
592    #[doc = "Bit 31 - Transfer Control Enable"]
593    #[inline(always)]
594    pub fn tce(&self) -> TCE_R {
595        TCE_R::new(((self.bits >> 31) & 1) != 0)
596    }
597}
598impl W {
599    #[doc = "Bits 0:1 - Work Mode Select"]
600    #[inline(always)]
601    #[must_use]
602    pub fn wms(&mut self) -> WMS_W<SPI_BATC_SPEC> {
603        WMS_W::new(self, 0)
604    }
605    #[doc = "Bits 2:3 - SPI Chip Select"]
606    #[inline(always)]
607    #[must_use]
608    pub fn ss_sel(&mut self) -> SS_SEL_W<SPI_BATC_SPEC> {
609        SS_SEL_W::new(self, 2)
610    }
611    #[doc = "Bit 5 - SPI Chip Select Signal Polarity Control"]
612    #[inline(always)]
613    #[must_use]
614    pub fn spol(&mut self) -> SPOL_W<SPI_BATC_SPEC> {
615        SPOL_W::new(self, 5)
616    }
617    #[doc = "Bit 6 - SS Output Owner Select"]
618    #[inline(always)]
619    #[must_use]
620    pub fn ss_owner(&mut self) -> SS_OWNER_W<SPI_BATC_SPEC> {
621        SS_OWNER_W::new(self, 6)
622    }
623    #[doc = "Bit 7"]
624    #[inline(always)]
625    #[must_use]
626    pub fn ss_level(&mut self) -> SS_LEVEL_W<SPI_BATC_SPEC> {
627        SS_LEVEL_W::new(self, 7)
628    }
629    #[doc = "Bits 8:13 - Configure the length of serial data frame of TX"]
630    #[inline(always)]
631    #[must_use]
632    pub fn tx_frm_len(&mut self) -> TX_FRM_LEN_W<SPI_BATC_SPEC> {
633        TX_FRM_LEN_W::new(self, 8)
634    }
635    #[doc = "Bits 16:21 - Configure the length of serial data frame of RX"]
636    #[inline(always)]
637    #[must_use]
638    pub fn rx_frm_len(&mut self) -> RX_FRM_LEN_W<SPI_BATC_SPEC> {
639        RX_FRM_LEN_W::new(self, 16)
640    }
641    #[doc = "Bit 24 - Transfer Bits Completed Interrupt Enable"]
642    #[inline(always)]
643    #[must_use]
644    pub fn tbc_int_en(&mut self) -> TBC_INT_EN_W<SPI_BATC_SPEC> {
645        TBC_INT_EN_W::new(self, 24)
646    }
647    #[doc = "Bit 25 - Transfer Bits Completed"]
648    #[inline(always)]
649    #[must_use]
650    pub fn tbc(&mut self) -> TBC_W<SPI_BATC_SPEC> {
651        TBC_W::new(self, 25)
652    }
653    #[doc = "Bit 30 - Master Sample Standard"]
654    #[inline(always)]
655    #[must_use]
656    pub fn msms(&mut self) -> MSMS_W<SPI_BATC_SPEC> {
657        MSMS_W::new(self, 30)
658    }
659    #[doc = "Bit 31 - Transfer Control Enable"]
660    #[inline(always)]
661    #[must_use]
662    pub fn tce(&mut self) -> TCE_W<SPI_BATC_SPEC> {
663        TCE_W::new(self, 31)
664    }
665    #[doc = r" Writes raw bits to the register."]
666    #[doc = r""]
667    #[doc = r" # Safety"]
668    #[doc = r""]
669    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
670    #[inline(always)]
671    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
672        self.bits = bits;
673        self
674    }
675}
676#[doc = "SPI Bit-Aligned Transfer Configure Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`spi_batc::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`spi_batc::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
677pub struct SPI_BATC_SPEC;
678impl crate::RegisterSpec for SPI_BATC_SPEC {
679    type Ux = u32;
680}
681#[doc = "`read()` method returns [`spi_batc::R`](R) reader structure"]
682impl crate::Readable for SPI_BATC_SPEC {}
683#[doc = "`write(|w| ..)` method takes [`spi_batc::W`](W) writer structure"]
684impl crate::Writable for SPI_BATC_SPEC {
685    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
686    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
687}
688#[doc = "`reset()` method sets spi_batc to value 0"]
689impl crate::Resettable for SPI_BATC_SPEC {
690    const RESET_VALUE: Self::Ux = 0;
691}
d1_pac/spi0/spi_batc.rs

d1_pac/spi0/
spi_batc.rs
