d1_pac/smhc/
smhc_status.rs

1#[doc = "Register `smhc_status` reader"]
2pub type R = crate::R<SMHC_STATUS_SPEC>;
3#[doc = "Field `fifo_rx_level` reader - FIFO RX Water Level Flag"]
4pub type FIFO_RX_LEVEL_R = crate::BitReader<FIFO_RX_LEVEL_A>;
5#[doc = "FIFO RX Water Level Flag\n\nValue on reset: 0"]
6#[derive(Clone, Copy, Debug, PartialEq, Eq)]
7pub enum FIFO_RX_LEVEL_A {
8    #[doc = "0: FIFO does not reach the receive trigger level"]
9    NOT_REACH = 0,
10    #[doc = "1: FIFO reaches the receive trigger level"]
11    REACH = 1,
12}
13impl From<FIFO_RX_LEVEL_A> for bool {
14    #[inline(always)]
15    fn from(variant: FIFO_RX_LEVEL_A) -> Self {
16        variant as u8 != 0
17    }
18}
19impl FIFO_RX_LEVEL_R {
20    #[doc = "Get enumerated values variant"]
21    #[inline(always)]
22    pub const fn variant(&self) -> FIFO_RX_LEVEL_A {
23        match self.bits {
24            false => FIFO_RX_LEVEL_A::NOT_REACH,
25            true => FIFO_RX_LEVEL_A::REACH,
26        }
27    }
28    #[doc = "FIFO does not reach the receive trigger level"]
29    #[inline(always)]
30    pub fn is_not_reach(&self) -> bool {
31        *self == FIFO_RX_LEVEL_A::NOT_REACH
32    }
33    #[doc = "FIFO reaches the receive trigger level"]
34    #[inline(always)]
35    pub fn is_reach(&self) -> bool {
36        *self == FIFO_RX_LEVEL_A::REACH
37    }
38}
39#[doc = "Field `fifo_tx_level` reader - FIFO TX Water Level Flag"]
40pub type FIFO_TX_LEVEL_R = crate::BitReader<FIFO_TX_LEVEL_A>;
41#[doc = "FIFO TX Water Level Flag\n\nValue on reset: 0"]
42#[derive(Clone, Copy, Debug, PartialEq, Eq)]
43pub enum FIFO_TX_LEVEL_A {
44    #[doc = "0: FIFO does not reach the transmit trigger level"]
45    NOT_REACH = 0,
46    #[doc = "1: FIFO reaches the transmit trigger level"]
47    REACH = 1,
48}
49impl From<FIFO_TX_LEVEL_A> for bool {
50    #[inline(always)]
51    fn from(variant: FIFO_TX_LEVEL_A) -> Self {
52        variant as u8 != 0
53    }
54}
55impl FIFO_TX_LEVEL_R {
56    #[doc = "Get enumerated values variant"]
57    #[inline(always)]
58    pub const fn variant(&self) -> FIFO_TX_LEVEL_A {
59        match self.bits {
60            false => FIFO_TX_LEVEL_A::NOT_REACH,
61            true => FIFO_TX_LEVEL_A::REACH,
62        }
63    }
64    #[doc = "FIFO does not reach the transmit trigger level"]
65    #[inline(always)]
66    pub fn is_not_reach(&self) -> bool {
67        *self == FIFO_TX_LEVEL_A::NOT_REACH
68    }
69    #[doc = "FIFO reaches the transmit trigger level"]
70    #[inline(always)]
71    pub fn is_reach(&self) -> bool {
72        *self == FIFO_TX_LEVEL_A::REACH
73    }
74}
75#[doc = "Field `fifo_empty` reader - FIFO Empty"]
76pub type FIFO_EMPTY_R = crate::BitReader<FIFO_EMPTY_A>;
77#[doc = "FIFO Empty\n\nValue on reset: 0"]
78#[derive(Clone, Copy, Debug, PartialEq, Eq)]
79pub enum FIFO_EMPTY_A {
80    #[doc = "0: FIFO is not empty"]
81    NOT_SEMPTY = 0,
82    #[doc = "1: FIFO is empty"]
83    EMPTY = 1,
84}
85impl From<FIFO_EMPTY_A> for bool {
86    #[inline(always)]
87    fn from(variant: FIFO_EMPTY_A) -> Self {
88        variant as u8 != 0
89    }
90}
91impl FIFO_EMPTY_R {
92    #[doc = "Get enumerated values variant"]
93    #[inline(always)]
94    pub const fn variant(&self) -> FIFO_EMPTY_A {
95        match self.bits {
96            false => FIFO_EMPTY_A::NOT_SEMPTY,
97            true => FIFO_EMPTY_A::EMPTY,
98        }
99    }
100    #[doc = "FIFO is not empty"]
101    #[inline(always)]
102    pub fn is_not_sempty(&self) -> bool {
103        *self == FIFO_EMPTY_A::NOT_SEMPTY
104    }
105    #[doc = "FIFO is empty"]
106    #[inline(always)]
107    pub fn is_empty(&self) -> bool {
108        *self == FIFO_EMPTY_A::EMPTY
109    }
110}
111#[doc = "Field `fifo_full` reader - sFIFO Full"]
112pub type FIFO_FULL_R = crate::BitReader<FIFO_FULL_A>;
113#[doc = "sFIFO Full\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum FIFO_FULL_A {
116    #[doc = "0: FIFO is not full"]
117    NOT_FULL = 0,
118    #[doc = "1: FIFO is full"]
119    FULL = 1,
120}
121impl From<FIFO_FULL_A> for bool {
122    #[inline(always)]
123    fn from(variant: FIFO_FULL_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl FIFO_FULL_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> FIFO_FULL_A {
131        match self.bits {
132            false => FIFO_FULL_A::NOT_FULL,
133            true => FIFO_FULL_A::FULL,
134        }
135    }
136    #[doc = "FIFO is not full"]
137    #[inline(always)]
138    pub fn is_not_full(&self) -> bool {
139        *self == FIFO_FULL_A::NOT_FULL
140    }
141    #[doc = "FIFO is full"]
142    #[inline(always)]
143    pub fn is_full(&self) -> bool {
144        *self == FIFO_FULL_A::FULL
145    }
146}
147#[doc = "Field `fsm_sta` reader - Command FSM States"]
148pub type FSM_STA_R = crate::FieldReader<FSM_STA_A>;
149#[doc = "Command FSM States\n\nValue on reset: 0"]
150#[derive(Clone, Copy, Debug, PartialEq, Eq)]
151#[repr(u8)]
152pub enum FSM_STA_A {
153    #[doc = "0: Idle"]
154    IDLE = 0,
155    #[doc = "1: Send init sequence"]
156    SIS = 1,
157    #[doc = "2: TX CMD start bit"]
158    TXCSB = 2,
159    #[doc = "3: TX CMD TX bit"]
160    TXCTB = 3,
161    #[doc = "4: TX CMD index + argument"]
162    TXCIA = 4,
163    #[doc = "5: TX CMD CRC7"]
164    TXCC = 5,
165    #[doc = "6: TX CMD end bit"]
166    TXCEB = 6,
167    #[doc = "7: RX response start bit"]
168    RXRSB = 7,
169    #[doc = "8: RX response IRQ responses"]
170    RXRIR = 8,
171    #[doc = "9: RX response TX bit"]
172    RXRTB = 9,
173    #[doc = "10: RX response CMD index"]
174    RXRCI = 10,
175    #[doc = "11: RX response data"]
176    RXRD = 11,
177    #[doc = "12: RX response CRC7"]
178    RXRC = 12,
179    #[doc = "13: RX response end bit"]
180    RXREB = 13,
181    #[doc = "14: CMD path wait NCC"]
182    CPWN = 14,
183    #[doc = "15: Wait; CMD-to-response turn around"]
184    WAIT = 15,
185}
186impl From<FSM_STA_A> for u8 {
187    #[inline(always)]
188    fn from(variant: FSM_STA_A) -> Self {
189        variant as _
190    }
191}
192impl crate::FieldSpec for FSM_STA_A {
193    type Ux = u8;
194}
195impl FSM_STA_R {
196    #[doc = "Get enumerated values variant"]
197    #[inline(always)]
198    pub const fn variant(&self) -> FSM_STA_A {
199        match self.bits {
200            0 => FSM_STA_A::IDLE,
201            1 => FSM_STA_A::SIS,
202            2 => FSM_STA_A::TXCSB,
203            3 => FSM_STA_A::TXCTB,
204            4 => FSM_STA_A::TXCIA,
205            5 => FSM_STA_A::TXCC,
206            6 => FSM_STA_A::TXCEB,
207            7 => FSM_STA_A::RXRSB,
208            8 => FSM_STA_A::RXRIR,
209            9 => FSM_STA_A::RXRTB,
210            10 => FSM_STA_A::RXRCI,
211            11 => FSM_STA_A::RXRD,
212            12 => FSM_STA_A::RXRC,
213            13 => FSM_STA_A::RXREB,
214            14 => FSM_STA_A::CPWN,
215            15 => FSM_STA_A::WAIT,
216            _ => unreachable!(),
217        }
218    }
219    #[doc = "Idle"]
220    #[inline(always)]
221    pub fn is_idle(&self) -> bool {
222        *self == FSM_STA_A::IDLE
223    }
224    #[doc = "Send init sequence"]
225    #[inline(always)]
226    pub fn is_sis(&self) -> bool {
227        *self == FSM_STA_A::SIS
228    }
229    #[doc = "TX CMD start bit"]
230    #[inline(always)]
231    pub fn is_txcsb(&self) -> bool {
232        *self == FSM_STA_A::TXCSB
233    }
234    #[doc = "TX CMD TX bit"]
235    #[inline(always)]
236    pub fn is_txctb(&self) -> bool {
237        *self == FSM_STA_A::TXCTB
238    }
239    #[doc = "TX CMD index + argument"]
240    #[inline(always)]
241    pub fn is_txcia(&self) -> bool {
242        *self == FSM_STA_A::TXCIA
243    }
244    #[doc = "TX CMD CRC7"]
245    #[inline(always)]
246    pub fn is_txcc(&self) -> bool {
247        *self == FSM_STA_A::TXCC
248    }
249    #[doc = "TX CMD end bit"]
250    #[inline(always)]
251    pub fn is_txceb(&self) -> bool {
252        *self == FSM_STA_A::TXCEB
253    }
254    #[doc = "RX response start bit"]
255    #[inline(always)]
256    pub fn is_rxrsb(&self) -> bool {
257        *self == FSM_STA_A::RXRSB
258    }
259    #[doc = "RX response IRQ responses"]
260    #[inline(always)]
261    pub fn is_rxrir(&self) -> bool {
262        *self == FSM_STA_A::RXRIR
263    }
264    #[doc = "RX response TX bit"]
265    #[inline(always)]
266    pub fn is_rxrtb(&self) -> bool {
267        *self == FSM_STA_A::RXRTB
268    }
269    #[doc = "RX response CMD index"]
270    #[inline(always)]
271    pub fn is_rxrci(&self) -> bool {
272        *self == FSM_STA_A::RXRCI
273    }
274    #[doc = "RX response data"]
275    #[inline(always)]
276    pub fn is_rxrd(&self) -> bool {
277        *self == FSM_STA_A::RXRD
278    }
279    #[doc = "RX response CRC7"]
280    #[inline(always)]
281    pub fn is_rxrc(&self) -> bool {
282        *self == FSM_STA_A::RXRC
283    }
284    #[doc = "RX response end bit"]
285    #[inline(always)]
286    pub fn is_rxreb(&self) -> bool {
287        *self == FSM_STA_A::RXREB
288    }
289    #[doc = "CMD path wait NCC"]
290    #[inline(always)]
291    pub fn is_cpwn(&self) -> bool {
292        *self == FSM_STA_A::CPWN
293    }
294    #[doc = "Wait; CMD-to-response turn around"]
295    #[inline(always)]
296    pub fn is_wait(&self) -> bool {
297        *self == FSM_STA_A::WAIT
298    }
299}
300#[doc = "Field `card_present` reader - Data\\[3\\] Statuss"]
301pub type CARD_PRESENT_R = crate::BitReader<CARD_PRESENT_A>;
302#[doc = "Data\\[3\\] Statuss\n\nValue on reset: 0"]
303#[derive(Clone, Copy, Debug, PartialEq, Eq)]
304pub enum CARD_PRESENT_A {
305    #[doc = "0: The card is not present"]
306    NOT_PRESENT = 0,
307    #[doc = "1: The card is present"]
308    PRESENT = 1,
309}
310impl From<CARD_PRESENT_A> for bool {
311    #[inline(always)]
312    fn from(variant: CARD_PRESENT_A) -> Self {
313        variant as u8 != 0
314    }
315}
316impl CARD_PRESENT_R {
317    #[doc = "Get enumerated values variant"]
318    #[inline(always)]
319    pub const fn variant(&self) -> CARD_PRESENT_A {
320        match self.bits {
321            false => CARD_PRESENT_A::NOT_PRESENT,
322            true => CARD_PRESENT_A::PRESENT,
323        }
324    }
325    #[doc = "The card is not present"]
326    #[inline(always)]
327    pub fn is_not_present(&self) -> bool {
328        *self == CARD_PRESENT_A::NOT_PRESENT
329    }
330    #[doc = "The card is present"]
331    #[inline(always)]
332    pub fn is_present(&self) -> bool {
333        *self == CARD_PRESENT_A::PRESENT
334    }
335}
336#[doc = "Field `card_busy` reader - Card Data Busy"]
337pub type CARD_BUSY_R = crate::BitReader<CARD_BUSY_A>;
338#[doc = "Card Data Busy\n\nValue on reset: 0"]
339#[derive(Clone, Copy, Debug, PartialEq, Eq)]
340pub enum CARD_BUSY_A {
341    #[doc = "0: Card data is not busy"]
342    NOT_BUSY = 0,
343    #[doc = "1: Card data is busy"]
344    BUSY = 1,
345}
346impl From<CARD_BUSY_A> for bool {
347    #[inline(always)]
348    fn from(variant: CARD_BUSY_A) -> Self {
349        variant as u8 != 0
350    }
351}
352impl CARD_BUSY_R {
353    #[doc = "Get enumerated values variant"]
354    #[inline(always)]
355    pub const fn variant(&self) -> CARD_BUSY_A {
356        match self.bits {
357            false => CARD_BUSY_A::NOT_BUSY,
358            true => CARD_BUSY_A::BUSY,
359        }
360    }
361    #[doc = "Card data is not busy"]
362    #[inline(always)]
363    pub fn is_not_busy(&self) -> bool {
364        *self == CARD_BUSY_A::NOT_BUSY
365    }
366    #[doc = "Card data is busy"]
367    #[inline(always)]
368    pub fn is_busy(&self) -> bool {
369        *self == CARD_BUSY_A::BUSY
370    }
371}
372#[doc = "Field `fsm_busy` reader - Data FSM Busy"]
373pub type FSM_BUSY_R = crate::BitReader;
374#[doc = "Field `resp_idx` reader - Response Index"]
375pub type RESP_IDX_R = crate::FieldReader;
376#[doc = "Field `fifo_level` reader - FIFO Level"]
377pub type FIFO_LEVEL_R = crate::FieldReader<u16>;
378#[doc = "Field `dma_req` reader - DMA Request"]
379pub type DMA_REQ_R = crate::BitReader;
380impl R {
381    #[doc = "Bit 0 - FIFO RX Water Level Flag"]
382    #[inline(always)]
383    pub fn fifo_rx_level(&self) -> FIFO_RX_LEVEL_R {
384        FIFO_RX_LEVEL_R::new((self.bits & 1) != 0)
385    }
386    #[doc = "Bit 1 - FIFO TX Water Level Flag"]
387    #[inline(always)]
388    pub fn fifo_tx_level(&self) -> FIFO_TX_LEVEL_R {
389        FIFO_TX_LEVEL_R::new(((self.bits >> 1) & 1) != 0)
390    }
391    #[doc = "Bit 2 - FIFO Empty"]
392    #[inline(always)]
393    pub fn fifo_empty(&self) -> FIFO_EMPTY_R {
394        FIFO_EMPTY_R::new(((self.bits >> 2) & 1) != 0)
395    }
396    #[doc = "Bit 3 - sFIFO Full"]
397    #[inline(always)]
398    pub fn fifo_full(&self) -> FIFO_FULL_R {
399        FIFO_FULL_R::new(((self.bits >> 3) & 1) != 0)
400    }
401    #[doc = "Bits 4:7 - Command FSM States"]
402    #[inline(always)]
403    pub fn fsm_sta(&self) -> FSM_STA_R {
404        FSM_STA_R::new(((self.bits >> 4) & 0x0f) as u8)
405    }
406    #[doc = "Bit 8 - Data\\[3\\] Statuss"]
407    #[inline(always)]
408    pub fn card_present(&self) -> CARD_PRESENT_R {
409        CARD_PRESENT_R::new(((self.bits >> 8) & 1) != 0)
410    }
411    #[doc = "Bit 9 - Card Data Busy"]
412    #[inline(always)]
413    pub fn card_busy(&self) -> CARD_BUSY_R {
414        CARD_BUSY_R::new(((self.bits >> 9) & 1) != 0)
415    }
416    #[doc = "Bit 10 - Data FSM Busy"]
417    #[inline(always)]
418    pub fn fsm_busy(&self) -> FSM_BUSY_R {
419        FSM_BUSY_R::new(((self.bits >> 10) & 1) != 0)
420    }
421    #[doc = "Bits 11:16 - Response Index"]
422    #[inline(always)]
423    pub fn resp_idx(&self) -> RESP_IDX_R {
424        RESP_IDX_R::new(((self.bits >> 11) & 0x3f) as u8)
425    }
426    #[doc = "Bits 17:25 - FIFO Level"]
427    #[inline(always)]
428    pub fn fifo_level(&self) -> FIFO_LEVEL_R {
429        FIFO_LEVEL_R::new(((self.bits >> 17) & 0x01ff) as u16)
430    }
431    #[doc = "Bit 31 - DMA Request"]
432    #[inline(always)]
433    pub fn dma_req(&self) -> DMA_REQ_R {
434        DMA_REQ_R::new(((self.bits >> 31) & 1) != 0)
435    }
436}
437#[doc = "Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
438pub struct SMHC_STATUS_SPEC;
439impl crate::RegisterSpec for SMHC_STATUS_SPEC {
440    type Ux = u32;
441}
442#[doc = "`read()` method returns [`smhc_status::R`](R) reader structure"]
443impl crate::Readable for SMHC_STATUS_SPEC {}
444#[doc = "`reset()` method sets smhc_status to value 0"]
445impl crate::Resettable for SMHC_STATUS_SPEC {
446    const RESET_VALUE: Self::Ux = 0;
447}
d1_pac/smhc/smhc_status.rs

d1_pac/smhc/
smhc_status.rs
