d1_pac/smhc/
smhc_rintsts.rs

1#[doc = "Register `smhc_rintsts` reader"]
2pub type R = crate::R<SMHC_RINTSTS_SPEC>;
3#[doc = "Register `smhc_rintsts` writer"]
4pub type W = crate::W<SMHC_RINTSTS_SPEC>;
5#[doc = "Field `re` reader - Response Error"]
6pub type RE_R = crate::BitReader;
7#[doc = "Field `re` writer - Response Error"]
8pub type RE_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `cc` reader - Command Complete"]
10pub type CC_R = crate::BitReader;
11#[doc = "Field `cc` writer - Command Complete"]
12pub type CC_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `dtc` reader - Data Transfer Complete"]
14pub type DTC_R = crate::BitReader;
15#[doc = "Field `dtc` writer - Data Transfer Complete"]
16pub type DTC_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `dtr` reader - Data Transmit Request"]
18pub type DTR_R = crate::BitReader;
19#[doc = "Field `dtr` writer - Data Transmit Request"]
20pub type DTR_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `drr` reader - Data Receive Request"]
22pub type DRR_R = crate::BitReader;
23#[doc = "Field `drr` writer - Data Receive Request"]
24pub type DRR_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `rce` reader - Response CRC Error"]
26pub type RCE_R = crate::BitReader;
27#[doc = "Field `rce` writer - Response CRC Error"]
28pub type RCE_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `dce` reader - Data CRC Error"]
30pub type DCE_R = crate::BitReader;
31#[doc = "Field `dce` writer - Data CRC Error"]
32pub type DCE_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `rto_back` reader - Response Timeout/Boot ACK Received"]
34pub type RTO_BACK_R = crate::BitReader;
35#[doc = "Field `rto_back` writer - Response Timeout/Boot ACK Received"]
36pub type RTO_BACK_W<'a, REG> = crate::BitWriter<'a, REG>;
37#[doc = "Field `dto_bds` reader - Data Timeout/Boot Data Start"]
38pub type DTO_BDS_R = crate::BitReader;
39#[doc = "Field `dto_bds` writer - Data Timeout/Boot Data Start"]
40pub type DTO_BDS_W<'a, REG> = crate::BitWriter<'a, REG>;
41#[doc = "Field `dsto_vsd` reader - Data Starvation Timeout/V1.8 Switch Done"]
42pub type DSTO_VSD_R = crate::BitReader;
43#[doc = "Field `dsto_vsd` writer - Data Starvation Timeout/V1.8 Switch Done"]
44pub type DSTO_VSD_W<'a, REG> = crate::BitWriter<'a, REG>;
45#[doc = "Field `fu_fo` reader - FIFO Underrun/Overflow"]
46pub type FU_FO_R = crate::BitReader;
47#[doc = "Field `fu_fo` writer - FIFO Underrun/Overflow"]
48pub type FU_FO_W<'a, REG> = crate::BitWriter<'a, REG>;
49#[doc = "Field `cb_iw` reader - Command Busy and Illegal Write"]
50pub type CB_IW_R = crate::BitReader;
51#[doc = "Field `cb_iw` writer - Command Busy and Illegal Write"]
52pub type CB_IW_W<'a, REG> = crate::BitWriter<'a, REG>;
53#[doc = "Field `dse_bc` reader - Data Start Error/Busy Clear"]
54pub type DSE_BC_R = crate::BitReader;
55#[doc = "Field `dse_bc` writer - Data Start Error/Busy Clear"]
56pub type DSE_BC_W<'a, REG> = crate::BitWriter<'a, REG>;
57#[doc = "Field `acd` reader - Auto Command Done"]
58pub type ACD_R = crate::BitReader;
59#[doc = "Field `acd` writer - Auto Command Done"]
60pub type ACD_W<'a, REG> = crate::BitWriter<'a, REG>;
61#[doc = "Field `dee` reader - Data End-bit Error"]
62pub type DEE_R = crate::BitReader;
63#[doc = "Field `dee` writer - Data End-bit Error"]
64pub type DEE_W<'a, REG> = crate::BitWriter<'a, REG>;
65#[doc = "Field `sdioi_int` reader - SDIO Interrupt"]
66pub type SDIOI_INT_R = crate::BitReader;
67#[doc = "Field `sdioi_int` writer - SDIO Interrupt"]
68pub type SDIOI_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
69#[doc = "Field `card_insert` reader - Card Inserted"]
70pub type CARD_INSERT_R = crate::BitReader;
71#[doc = "Field `card_insert` writer - Card Inserted"]
72pub type CARD_INSERT_W<'a, REG> = crate::BitWriter<'a, REG>;
73#[doc = "Field `card_removal` reader - Card Removed"]
74pub type CARD_REMOVAL_R = crate::BitReader;
75#[doc = "Field `card_removal` writer - Card Removed"]
76pub type CARD_REMOVAL_W<'a, REG> = crate::BitWriter<'a, REG>;
77impl R {
78    #[doc = "Bit 1 - Response Error"]
79    #[inline(always)]
80    pub fn re(&self) -> RE_R {
81        RE_R::new(((self.bits >> 1) & 1) != 0)
82    }
83    #[doc = "Bit 2 - Command Complete"]
84    #[inline(always)]
85    pub fn cc(&self) -> CC_R {
86        CC_R::new(((self.bits >> 2) & 1) != 0)
87    }
88    #[doc = "Bit 3 - Data Transfer Complete"]
89    #[inline(always)]
90    pub fn dtc(&self) -> DTC_R {
91        DTC_R::new(((self.bits >> 3) & 1) != 0)
92    }
93    #[doc = "Bit 4 - Data Transmit Request"]
94    #[inline(always)]
95    pub fn dtr(&self) -> DTR_R {
96        DTR_R::new(((self.bits >> 4) & 1) != 0)
97    }
98    #[doc = "Bit 5 - Data Receive Request"]
99    #[inline(always)]
100    pub fn drr(&self) -> DRR_R {
101        DRR_R::new(((self.bits >> 5) & 1) != 0)
102    }
103    #[doc = "Bit 6 - Response CRC Error"]
104    #[inline(always)]
105    pub fn rce(&self) -> RCE_R {
106        RCE_R::new(((self.bits >> 6) & 1) != 0)
107    }
108    #[doc = "Bit 7 - Data CRC Error"]
109    #[inline(always)]
110    pub fn dce(&self) -> DCE_R {
111        DCE_R::new(((self.bits >> 7) & 1) != 0)
112    }
113    #[doc = "Bit 8 - Response Timeout/Boot ACK Received"]
114    #[inline(always)]
115    pub fn rto_back(&self) -> RTO_BACK_R {
116        RTO_BACK_R::new(((self.bits >> 8) & 1) != 0)
117    }
118    #[doc = "Bit 9 - Data Timeout/Boot Data Start"]
119    #[inline(always)]
120    pub fn dto_bds(&self) -> DTO_BDS_R {
121        DTO_BDS_R::new(((self.bits >> 9) & 1) != 0)
122    }
123    #[doc = "Bit 10 - Data Starvation Timeout/V1.8 Switch Done"]
124    #[inline(always)]
125    pub fn dsto_vsd(&self) -> DSTO_VSD_R {
126        DSTO_VSD_R::new(((self.bits >> 10) & 1) != 0)
127    }
128    #[doc = "Bit 11 - FIFO Underrun/Overflow"]
129    #[inline(always)]
130    pub fn fu_fo(&self) -> FU_FO_R {
131        FU_FO_R::new(((self.bits >> 11) & 1) != 0)
132    }
133    #[doc = "Bit 12 - Command Busy and Illegal Write"]
134    #[inline(always)]
135    pub fn cb_iw(&self) -> CB_IW_R {
136        CB_IW_R::new(((self.bits >> 12) & 1) != 0)
137    }
138    #[doc = "Bit 13 - Data Start Error/Busy Clear"]
139    #[inline(always)]
140    pub fn dse_bc(&self) -> DSE_BC_R {
141        DSE_BC_R::new(((self.bits >> 13) & 1) != 0)
142    }
143    #[doc = "Bit 14 - Auto Command Done"]
144    #[inline(always)]
145    pub fn acd(&self) -> ACD_R {
146        ACD_R::new(((self.bits >> 14) & 1) != 0)
147    }
148    #[doc = "Bit 15 - Data End-bit Error"]
149    #[inline(always)]
150    pub fn dee(&self) -> DEE_R {
151        DEE_R::new(((self.bits >> 15) & 1) != 0)
152    }
153    #[doc = "Bit 16 - SDIO Interrupt"]
154    #[inline(always)]
155    pub fn sdioi_int(&self) -> SDIOI_INT_R {
156        SDIOI_INT_R::new(((self.bits >> 16) & 1) != 0)
157    }
158    #[doc = "Bit 30 - Card Inserted"]
159    #[inline(always)]
160    pub fn card_insert(&self) -> CARD_INSERT_R {
161        CARD_INSERT_R::new(((self.bits >> 30) & 1) != 0)
162    }
163    #[doc = "Bit 31 - Card Removed"]
164    #[inline(always)]
165    pub fn card_removal(&self) -> CARD_REMOVAL_R {
166        CARD_REMOVAL_R::new(((self.bits >> 31) & 1) != 0)
167    }
168}
169impl W {
170    #[doc = "Bit 1 - Response Error"]
171    #[inline(always)]
172    #[must_use]
173    pub fn re(&mut self) -> RE_W<SMHC_RINTSTS_SPEC> {
174        RE_W::new(self, 1)
175    }
176    #[doc = "Bit 2 - Command Complete"]
177    #[inline(always)]
178    #[must_use]
179    pub fn cc(&mut self) -> CC_W<SMHC_RINTSTS_SPEC> {
180        CC_W::new(self, 2)
181    }
182    #[doc = "Bit 3 - Data Transfer Complete"]
183    #[inline(always)]
184    #[must_use]
185    pub fn dtc(&mut self) -> DTC_W<SMHC_RINTSTS_SPEC> {
186        DTC_W::new(self, 3)
187    }
188    #[doc = "Bit 4 - Data Transmit Request"]
189    #[inline(always)]
190    #[must_use]
191    pub fn dtr(&mut self) -> DTR_W<SMHC_RINTSTS_SPEC> {
192        DTR_W::new(self, 4)
193    }
194    #[doc = "Bit 5 - Data Receive Request"]
195    #[inline(always)]
196    #[must_use]
197    pub fn drr(&mut self) -> DRR_W<SMHC_RINTSTS_SPEC> {
198        DRR_W::new(self, 5)
199    }
200    #[doc = "Bit 6 - Response CRC Error"]
201    #[inline(always)]
202    #[must_use]
203    pub fn rce(&mut self) -> RCE_W<SMHC_RINTSTS_SPEC> {
204        RCE_W::new(self, 6)
205    }
206    #[doc = "Bit 7 - Data CRC Error"]
207    #[inline(always)]
208    #[must_use]
209    pub fn dce(&mut self) -> DCE_W<SMHC_RINTSTS_SPEC> {
210        DCE_W::new(self, 7)
211    }
212    #[doc = "Bit 8 - Response Timeout/Boot ACK Received"]
213    #[inline(always)]
214    #[must_use]
215    pub fn rto_back(&mut self) -> RTO_BACK_W<SMHC_RINTSTS_SPEC> {
216        RTO_BACK_W::new(self, 8)
217    }
218    #[doc = "Bit 9 - Data Timeout/Boot Data Start"]
219    #[inline(always)]
220    #[must_use]
221    pub fn dto_bds(&mut self) -> DTO_BDS_W<SMHC_RINTSTS_SPEC> {
222        DTO_BDS_W::new(self, 9)
223    }
224    #[doc = "Bit 10 - Data Starvation Timeout/V1.8 Switch Done"]
225    #[inline(always)]
226    #[must_use]
227    pub fn dsto_vsd(&mut self) -> DSTO_VSD_W<SMHC_RINTSTS_SPEC> {
228        DSTO_VSD_W::new(self, 10)
229    }
230    #[doc = "Bit 11 - FIFO Underrun/Overflow"]
231    #[inline(always)]
232    #[must_use]
233    pub fn fu_fo(&mut self) -> FU_FO_W<SMHC_RINTSTS_SPEC> {
234        FU_FO_W::new(self, 11)
235    }
236    #[doc = "Bit 12 - Command Busy and Illegal Write"]
237    #[inline(always)]
238    #[must_use]
239    pub fn cb_iw(&mut self) -> CB_IW_W<SMHC_RINTSTS_SPEC> {
240        CB_IW_W::new(self, 12)
241    }
242    #[doc = "Bit 13 - Data Start Error/Busy Clear"]
243    #[inline(always)]
244    #[must_use]
245    pub fn dse_bc(&mut self) -> DSE_BC_W<SMHC_RINTSTS_SPEC> {
246        DSE_BC_W::new(self, 13)
247    }
248    #[doc = "Bit 14 - Auto Command Done"]
249    #[inline(always)]
250    #[must_use]
251    pub fn acd(&mut self) -> ACD_W<SMHC_RINTSTS_SPEC> {
252        ACD_W::new(self, 14)
253    }
254    #[doc = "Bit 15 - Data End-bit Error"]
255    #[inline(always)]
256    #[must_use]
257    pub fn dee(&mut self) -> DEE_W<SMHC_RINTSTS_SPEC> {
258        DEE_W::new(self, 15)
259    }
260    #[doc = "Bit 16 - SDIO Interrupt"]
261    #[inline(always)]
262    #[must_use]
263    pub fn sdioi_int(&mut self) -> SDIOI_INT_W<SMHC_RINTSTS_SPEC> {
264        SDIOI_INT_W::new(self, 16)
265    }
266    #[doc = "Bit 30 - Card Inserted"]
267    #[inline(always)]
268    #[must_use]
269    pub fn card_insert(&mut self) -> CARD_INSERT_W<SMHC_RINTSTS_SPEC> {
270        CARD_INSERT_W::new(self, 30)
271    }
272    #[doc = "Bit 31 - Card Removed"]
273    #[inline(always)]
274    #[must_use]
275    pub fn card_removal(&mut self) -> CARD_REMOVAL_W<SMHC_RINTSTS_SPEC> {
276        CARD_REMOVAL_W::new(self, 31)
277    }
278    #[doc = r" Writes raw bits to the register."]
279    #[doc = r""]
280    #[doc = r" # Safety"]
281    #[doc = r""]
282    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
283    #[inline(always)]
284    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
285        self.bits = bits;
286        self
287    }
288}
289#[doc = "Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_rintsts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_rintsts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
290pub struct SMHC_RINTSTS_SPEC;
291impl crate::RegisterSpec for SMHC_RINTSTS_SPEC {
292    type Ux = u32;
293}
294#[doc = "`read()` method returns [`smhc_rintsts::R`](R) reader structure"]
295impl crate::Readable for SMHC_RINTSTS_SPEC {}
296#[doc = "`write(|w| ..)` method takes [`smhc_rintsts::W`](W) writer structure"]
297impl crate::Writable for SMHC_RINTSTS_SPEC {
298    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
299    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
300}
301#[doc = "`reset()` method sets smhc_rintsts to value 0"]
302impl crate::Resettable for SMHC_RINTSTS_SPEC {
303    const RESET_VALUE: Self::Ux = 0;
304}
d1_pac/smhc/smhc_rintsts.rs

d1_pac/smhc/
smhc_rintsts.rs
