d1_pac/smhc/
smhc_ntsr.rs

1#[doc = "Register `smhc_ntsr` reader"]
2pub type R = crate::R<SMHC_NTSR_SPEC>;
3#[doc = "Register `smhc_ntsr` writer"]
4pub type W = crate::W<SMHC_NTSR_SPEC>;
5#[doc = "Field `hs400_new_sample_en` reader - "]
6pub type HS400_NEW_SAMPLE_EN_R = crate::BitReader<HS400_NEW_SAMPLE_EN_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum HS400_NEW_SAMPLE_EN_A {
10    #[doc = "0: Disable hs400 new sample method"]
11    DISABLE = 0,
12    #[doc = "1: Enable hs400 new sample method"]
13    ENABLE = 1,
14}
15impl From<HS400_NEW_SAMPLE_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: HS400_NEW_SAMPLE_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl HS400_NEW_SAMPLE_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> HS400_NEW_SAMPLE_EN_A {
25        match self.bits {
26            false => HS400_NEW_SAMPLE_EN_A::DISABLE,
27            true => HS400_NEW_SAMPLE_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Disable hs400 new sample method"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == HS400_NEW_SAMPLE_EN_A::DISABLE
34    }
35    #[doc = "Enable hs400 new sample method"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == HS400_NEW_SAMPLE_EN_A::ENABLE
39    }
40}
41#[doc = "Field `hs400_new_sample_en` writer - "]
42pub type HS400_NEW_SAMPLE_EN_W<'a, REG> = crate::BitWriter<'a, REG, HS400_NEW_SAMPLE_EN_A>;
43impl<'a, REG> HS400_NEW_SAMPLE_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable hs400 new sample method"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(HS400_NEW_SAMPLE_EN_A::DISABLE)
51    }
52    #[doc = "Enable hs400 new sample method"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(HS400_NEW_SAMPLE_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `cmd_sample_timing_phase` reader - "]
59pub type CMD_SAMPLE_TIMING_PHASE_R = crate::FieldReader<CMD_SAMPLE_TIMING_PHASE_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u8)]
63pub enum CMD_SAMPLE_TIMING_PHASE_A {
64    #[doc = "0: Sample timing phase offset 90"]
65    O90 = 0,
66    #[doc = "1: Sample timing phase offset 180"]
67    O180 = 1,
68    #[doc = "2: Sample timing phase offset 270"]
69    O270 = 2,
70    #[doc = "3: Ignore"]
71    O0 = 3,
72}
73impl From<CMD_SAMPLE_TIMING_PHASE_A> for u8 {
74    #[inline(always)]
75    fn from(variant: CMD_SAMPLE_TIMING_PHASE_A) -> Self {
76        variant as _
77    }
78}
79impl crate::FieldSpec for CMD_SAMPLE_TIMING_PHASE_A {
80    type Ux = u8;
81}
82impl CMD_SAMPLE_TIMING_PHASE_R {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub const fn variant(&self) -> CMD_SAMPLE_TIMING_PHASE_A {
86        match self.bits {
87            0 => CMD_SAMPLE_TIMING_PHASE_A::O90,
88            1 => CMD_SAMPLE_TIMING_PHASE_A::O180,
89            2 => CMD_SAMPLE_TIMING_PHASE_A::O270,
90            3 => CMD_SAMPLE_TIMING_PHASE_A::O0,
91            _ => unreachable!(),
92        }
93    }
94    #[doc = "Sample timing phase offset 90"]
95    #[inline(always)]
96    pub fn is_o90(&self) -> bool {
97        *self == CMD_SAMPLE_TIMING_PHASE_A::O90
98    }
99    #[doc = "Sample timing phase offset 180"]
100    #[inline(always)]
101    pub fn is_o180(&self) -> bool {
102        *self == CMD_SAMPLE_TIMING_PHASE_A::O180
103    }
104    #[doc = "Sample timing phase offset 270"]
105    #[inline(always)]
106    pub fn is_o270(&self) -> bool {
107        *self == CMD_SAMPLE_TIMING_PHASE_A::O270
108    }
109    #[doc = "Ignore"]
110    #[inline(always)]
111    pub fn is_o0(&self) -> bool {
112        *self == CMD_SAMPLE_TIMING_PHASE_A::O0
113    }
114}
115#[doc = "Field `cmd_sample_timing_phase` writer - "]
116pub type CMD_SAMPLE_TIMING_PHASE_W<'a, REG> =
117    crate::FieldWriterSafe<'a, REG, 2, CMD_SAMPLE_TIMING_PHASE_A>;
118impl<'a, REG> CMD_SAMPLE_TIMING_PHASE_W<'a, REG>
119where
120    REG: crate::Writable + crate::RegisterSpec,
121    REG::Ux: From<u8>,
122{
123    #[doc = "Sample timing phase offset 90"]
124    #[inline(always)]
125    pub fn o90(self) -> &'a mut crate::W<REG> {
126        self.variant(CMD_SAMPLE_TIMING_PHASE_A::O90)
127    }
128    #[doc = "Sample timing phase offset 180"]
129    #[inline(always)]
130    pub fn o180(self) -> &'a mut crate::W<REG> {
131        self.variant(CMD_SAMPLE_TIMING_PHASE_A::O180)
132    }
133    #[doc = "Sample timing phase offset 270"]
134    #[inline(always)]
135    pub fn o270(self) -> &'a mut crate::W<REG> {
136        self.variant(CMD_SAMPLE_TIMING_PHASE_A::O270)
137    }
138    #[doc = "Ignore"]
139    #[inline(always)]
140    pub fn o0(self) -> &'a mut crate::W<REG> {
141        self.variant(CMD_SAMPLE_TIMING_PHASE_A::O0)
142    }
143}
144#[doc = "Field `dat_sample_timing_phase` reader - "]
145pub type DAT_SAMPLE_TIMING_PHASE_R = crate::FieldReader<DAT_SAMPLE_TIMING_PHASE_A>;
146#[doc = "\n\nValue on reset: 0"]
147#[derive(Clone, Copy, Debug, PartialEq, Eq)]
148#[repr(u8)]
149pub enum DAT_SAMPLE_TIMING_PHASE_A {
150    #[doc = "0: Sample timing phase offset 90"]
151    O90 = 0,
152    #[doc = "1: Sample timing phase offset 180"]
153    O180 = 1,
154    #[doc = "2: Sample timing phase offset 270"]
155    O270 = 2,
156    #[doc = "3: Sample timing phase offset 0 (only for SD2 hs400 mode)"]
157    O0 = 3,
158}
159impl From<DAT_SAMPLE_TIMING_PHASE_A> for u8 {
160    #[inline(always)]
161    fn from(variant: DAT_SAMPLE_TIMING_PHASE_A) -> Self {
162        variant as _
163    }
164}
165impl crate::FieldSpec for DAT_SAMPLE_TIMING_PHASE_A {
166    type Ux = u8;
167}
168impl DAT_SAMPLE_TIMING_PHASE_R {
169    #[doc = "Get enumerated values variant"]
170    #[inline(always)]
171    pub const fn variant(&self) -> DAT_SAMPLE_TIMING_PHASE_A {
172        match self.bits {
173            0 => DAT_SAMPLE_TIMING_PHASE_A::O90,
174            1 => DAT_SAMPLE_TIMING_PHASE_A::O180,
175            2 => DAT_SAMPLE_TIMING_PHASE_A::O270,
176            3 => DAT_SAMPLE_TIMING_PHASE_A::O0,
177            _ => unreachable!(),
178        }
179    }
180    #[doc = "Sample timing phase offset 90"]
181    #[inline(always)]
182    pub fn is_o90(&self) -> bool {
183        *self == DAT_SAMPLE_TIMING_PHASE_A::O90
184    }
185    #[doc = "Sample timing phase offset 180"]
186    #[inline(always)]
187    pub fn is_o180(&self) -> bool {
188        *self == DAT_SAMPLE_TIMING_PHASE_A::O180
189    }
190    #[doc = "Sample timing phase offset 270"]
191    #[inline(always)]
192    pub fn is_o270(&self) -> bool {
193        *self == DAT_SAMPLE_TIMING_PHASE_A::O270
194    }
195    #[doc = "Sample timing phase offset 0 (only for SD2 hs400 mode)"]
196    #[inline(always)]
197    pub fn is_o0(&self) -> bool {
198        *self == DAT_SAMPLE_TIMING_PHASE_A::O0
199    }
200}
201#[doc = "Field `dat_sample_timing_phase` writer - "]
202pub type DAT_SAMPLE_TIMING_PHASE_W<'a, REG> =
203    crate::FieldWriterSafe<'a, REG, 2, DAT_SAMPLE_TIMING_PHASE_A>;
204impl<'a, REG> DAT_SAMPLE_TIMING_PHASE_W<'a, REG>
205where
206    REG: crate::Writable + crate::RegisterSpec,
207    REG::Ux: From<u8>,
208{
209    #[doc = "Sample timing phase offset 90"]
210    #[inline(always)]
211    pub fn o90(self) -> &'a mut crate::W<REG> {
212        self.variant(DAT_SAMPLE_TIMING_PHASE_A::O90)
213    }
214    #[doc = "Sample timing phase offset 180"]
215    #[inline(always)]
216    pub fn o180(self) -> &'a mut crate::W<REG> {
217        self.variant(DAT_SAMPLE_TIMING_PHASE_A::O180)
218    }
219    #[doc = "Sample timing phase offset 270"]
220    #[inline(always)]
221    pub fn o270(self) -> &'a mut crate::W<REG> {
222        self.variant(DAT_SAMPLE_TIMING_PHASE_A::O270)
223    }
224    #[doc = "Sample timing phase offset 0 (only for SD2 hs400 mode)"]
225    #[inline(always)]
226    pub fn o0(self) -> &'a mut crate::W<REG> {
227        self.variant(DAT_SAMPLE_TIMING_PHASE_A::O0)
228    }
229}
230#[doc = "Field `cmd_send_rx_phase_clr` reader - Clear command rx phase before sending the command"]
231pub type CMD_SEND_RX_PHASE_CLR_R = crate::BitReader<CMD_SEND_RX_PHASE_CLR_A>;
232#[doc = "Clear command rx phase before sending the command\n\nValue on reset: 0"]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234pub enum CMD_SEND_RX_PHASE_CLR_A {
235    #[doc = "0: Disabled"]
236    DISABLED = 0,
237    #[doc = "1: Enabled"]
238    ENABLED = 1,
239}
240impl From<CMD_SEND_RX_PHASE_CLR_A> for bool {
241    #[inline(always)]
242    fn from(variant: CMD_SEND_RX_PHASE_CLR_A) -> Self {
243        variant as u8 != 0
244    }
245}
246impl CMD_SEND_RX_PHASE_CLR_R {
247    #[doc = "Get enumerated values variant"]
248    #[inline(always)]
249    pub const fn variant(&self) -> CMD_SEND_RX_PHASE_CLR_A {
250        match self.bits {
251            false => CMD_SEND_RX_PHASE_CLR_A::DISABLED,
252            true => CMD_SEND_RX_PHASE_CLR_A::ENABLED,
253        }
254    }
255    #[doc = "Disabled"]
256    #[inline(always)]
257    pub fn is_disabled(&self) -> bool {
258        *self == CMD_SEND_RX_PHASE_CLR_A::DISABLED
259    }
260    #[doc = "Enabled"]
261    #[inline(always)]
262    pub fn is_enabled(&self) -> bool {
263        *self == CMD_SEND_RX_PHASE_CLR_A::ENABLED
264    }
265}
266#[doc = "Field `cmd_send_rx_phase_clr` writer - Clear command rx phase before sending the command"]
267pub type CMD_SEND_RX_PHASE_CLR_W<'a, REG> = crate::BitWriter<'a, REG, CMD_SEND_RX_PHASE_CLR_A>;
268impl<'a, REG> CMD_SEND_RX_PHASE_CLR_W<'a, REG>
269where
270    REG: crate::Writable + crate::RegisterSpec,
271{
272    #[doc = "Disabled"]
273    #[inline(always)]
274    pub fn disabled(self) -> &'a mut crate::W<REG> {
275        self.variant(CMD_SEND_RX_PHASE_CLR_A::DISABLED)
276    }
277    #[doc = "Enabled"]
278    #[inline(always)]
279    pub fn enabled(self) -> &'a mut crate::W<REG> {
280        self.variant(CMD_SEND_RX_PHASE_CLR_A::ENABLED)
281    }
282}
283#[doc = "Field `dat_recv_rx_phase_clr` reader - Clear the input phase of data lines before receiving the data"]
284pub type DAT_RECV_RX_PHASE_CLR_R = crate::BitReader<DAT_RECV_RX_PHASE_CLR_A>;
285#[doc = "Clear the input phase of data lines before receiving the data\n\nValue on reset: 0"]
286#[derive(Clone, Copy, Debug, PartialEq, Eq)]
287pub enum DAT_RECV_RX_PHASE_CLR_A {
288    #[doc = "0: Disabled"]
289    DISABLED = 0,
290    #[doc = "1: Enabled"]
291    ENABLED = 1,
292}
293impl From<DAT_RECV_RX_PHASE_CLR_A> for bool {
294    #[inline(always)]
295    fn from(variant: DAT_RECV_RX_PHASE_CLR_A) -> Self {
296        variant as u8 != 0
297    }
298}
299impl DAT_RECV_RX_PHASE_CLR_R {
300    #[doc = "Get enumerated values variant"]
301    #[inline(always)]
302    pub const fn variant(&self) -> DAT_RECV_RX_PHASE_CLR_A {
303        match self.bits {
304            false => DAT_RECV_RX_PHASE_CLR_A::DISABLED,
305            true => DAT_RECV_RX_PHASE_CLR_A::ENABLED,
306        }
307    }
308    #[doc = "Disabled"]
309    #[inline(always)]
310    pub fn is_disabled(&self) -> bool {
311        *self == DAT_RECV_RX_PHASE_CLR_A::DISABLED
312    }
313    #[doc = "Enabled"]
314    #[inline(always)]
315    pub fn is_enabled(&self) -> bool {
316        *self == DAT_RECV_RX_PHASE_CLR_A::ENABLED
317    }
318}
319#[doc = "Field `dat_recv_rx_phase_clr` writer - Clear the input phase of data lines before receiving the data"]
320pub type DAT_RECV_RX_PHASE_CLR_W<'a, REG> = crate::BitWriter<'a, REG, DAT_RECV_RX_PHASE_CLR_A>;
321impl<'a, REG> DAT_RECV_RX_PHASE_CLR_W<'a, REG>
322where
323    REG: crate::Writable + crate::RegisterSpec,
324{
325    #[doc = "Disabled"]
326    #[inline(always)]
327    pub fn disabled(self) -> &'a mut crate::W<REG> {
328        self.variant(DAT_RECV_RX_PHASE_CLR_A::DISABLED)
329    }
330    #[doc = "Enabled"]
331    #[inline(always)]
332    pub fn enabled(self) -> &'a mut crate::W<REG> {
333        self.variant(DAT_RECV_RX_PHASE_CLR_A::ENABLED)
334    }
335}
336#[doc = "Field `dat_trans_rx_phase_clr` reader - Clear the input phase of data lines before transferring the data"]
337pub type DAT_TRANS_RX_PHASE_CLR_R = crate::BitReader<DAT_TRANS_RX_PHASE_CLR_A>;
338#[doc = "Clear the input phase of data lines before transferring the data\n\nValue on reset: 0"]
339#[derive(Clone, Copy, Debug, PartialEq, Eq)]
340pub enum DAT_TRANS_RX_PHASE_CLR_A {
341    #[doc = "0: Disabled"]
342    DISABLED = 0,
343    #[doc = "1: Enabled"]
344    ENABLED = 1,
345}
346impl From<DAT_TRANS_RX_PHASE_CLR_A> for bool {
347    #[inline(always)]
348    fn from(variant: DAT_TRANS_RX_PHASE_CLR_A) -> Self {
349        variant as u8 != 0
350    }
351}
352impl DAT_TRANS_RX_PHASE_CLR_R {
353    #[doc = "Get enumerated values variant"]
354    #[inline(always)]
355    pub const fn variant(&self) -> DAT_TRANS_RX_PHASE_CLR_A {
356        match self.bits {
357            false => DAT_TRANS_RX_PHASE_CLR_A::DISABLED,
358            true => DAT_TRANS_RX_PHASE_CLR_A::ENABLED,
359        }
360    }
361    #[doc = "Disabled"]
362    #[inline(always)]
363    pub fn is_disabled(&self) -> bool {
364        *self == DAT_TRANS_RX_PHASE_CLR_A::DISABLED
365    }
366    #[doc = "Enabled"]
367    #[inline(always)]
368    pub fn is_enabled(&self) -> bool {
369        *self == DAT_TRANS_RX_PHASE_CLR_A::ENABLED
370    }
371}
372#[doc = "Field `dat_trans_rx_phase_clr` writer - Clear the input phase of data lines before transferring the data"]
373pub type DAT_TRANS_RX_PHASE_CLR_W<'a, REG> = crate::BitWriter<'a, REG, DAT_TRANS_RX_PHASE_CLR_A>;
374impl<'a, REG> DAT_TRANS_RX_PHASE_CLR_W<'a, REG>
375where
376    REG: crate::Writable + crate::RegisterSpec,
377{
378    #[doc = "Disabled"]
379    #[inline(always)]
380    pub fn disabled(self) -> &'a mut crate::W<REG> {
381        self.variant(DAT_TRANS_RX_PHASE_CLR_A::DISABLED)
382    }
383    #[doc = "Enabled"]
384    #[inline(always)]
385    pub fn enabled(self) -> &'a mut crate::W<REG> {
386        self.variant(DAT_TRANS_RX_PHASE_CLR_A::ENABLED)
387    }
388}
389#[doc = "Field `dat_crc_status_rx_phase_clr` reader - Clear the input phase of data lines before receiving the CRC status"]
390pub type DAT_CRC_STATUS_RX_PHASE_CLR_R = crate::BitReader<DAT_CRC_STATUS_RX_PHASE_CLR_A>;
391#[doc = "Clear the input phase of data lines before receiving the CRC status\n\nValue on reset: 0"]
392#[derive(Clone, Copy, Debug, PartialEq, Eq)]
393pub enum DAT_CRC_STATUS_RX_PHASE_CLR_A {
394    #[doc = "0: Disabled"]
395    DISABLED = 0,
396    #[doc = "1: Enabled"]
397    ENABLED = 1,
398}
399impl From<DAT_CRC_STATUS_RX_PHASE_CLR_A> for bool {
400    #[inline(always)]
401    fn from(variant: DAT_CRC_STATUS_RX_PHASE_CLR_A) -> Self {
402        variant as u8 != 0
403    }
404}
405impl DAT_CRC_STATUS_RX_PHASE_CLR_R {
406    #[doc = "Get enumerated values variant"]
407    #[inline(always)]
408    pub const fn variant(&self) -> DAT_CRC_STATUS_RX_PHASE_CLR_A {
409        match self.bits {
410            false => DAT_CRC_STATUS_RX_PHASE_CLR_A::DISABLED,
411            true => DAT_CRC_STATUS_RX_PHASE_CLR_A::ENABLED,
412        }
413    }
414    #[doc = "Disabled"]
415    #[inline(always)]
416    pub fn is_disabled(&self) -> bool {
417        *self == DAT_CRC_STATUS_RX_PHASE_CLR_A::DISABLED
418    }
419    #[doc = "Enabled"]
420    #[inline(always)]
421    pub fn is_enabled(&self) -> bool {
422        *self == DAT_CRC_STATUS_RX_PHASE_CLR_A::ENABLED
423    }
424}
425#[doc = "Field `dat_crc_status_rx_phase_clr` writer - Clear the input phase of data lines before receiving the CRC status"]
426pub type DAT_CRC_STATUS_RX_PHASE_CLR_W<'a, REG> =
427    crate::BitWriter<'a, REG, DAT_CRC_STATUS_RX_PHASE_CLR_A>;
428impl<'a, REG> DAT_CRC_STATUS_RX_PHASE_CLR_W<'a, REG>
429where
430    REG: crate::Writable + crate::RegisterSpec,
431{
432    #[doc = "Disabled"]
433    #[inline(always)]
434    pub fn disabled(self) -> &'a mut crate::W<REG> {
435        self.variant(DAT_CRC_STATUS_RX_PHASE_CLR_A::DISABLED)
436    }
437    #[doc = "Enabled"]
438    #[inline(always)]
439    pub fn enabled(self) -> &'a mut crate::W<REG> {
440        self.variant(DAT_CRC_STATUS_RX_PHASE_CLR_A::ENABLED)
441    }
442}
443#[doc = "Field `cmd_dat_rx_phase_clr` reader - Clear the input phase of command lines and data lines during the update clock operation"]
444pub type CMD_DAT_RX_PHASE_CLR_R = crate::BitReader<CMD_DAT_RX_PHASE_CLR_A>;
445#[doc = "Clear the input phase of command lines and data lines during the update clock operation\n\nValue on reset: 0"]
446#[derive(Clone, Copy, Debug, PartialEq, Eq)]
447pub enum CMD_DAT_RX_PHASE_CLR_A {
448    #[doc = "0: Disabled"]
449    DISABLED = 0,
450    #[doc = "1: Enabled"]
451    ENABLED = 1,
452}
453impl From<CMD_DAT_RX_PHASE_CLR_A> for bool {
454    #[inline(always)]
455    fn from(variant: CMD_DAT_RX_PHASE_CLR_A) -> Self {
456        variant as u8 != 0
457    }
458}
459impl CMD_DAT_RX_PHASE_CLR_R {
460    #[doc = "Get enumerated values variant"]
461    #[inline(always)]
462    pub const fn variant(&self) -> CMD_DAT_RX_PHASE_CLR_A {
463        match self.bits {
464            false => CMD_DAT_RX_PHASE_CLR_A::DISABLED,
465            true => CMD_DAT_RX_PHASE_CLR_A::ENABLED,
466        }
467    }
468    #[doc = "Disabled"]
469    #[inline(always)]
470    pub fn is_disabled(&self) -> bool {
471        *self == CMD_DAT_RX_PHASE_CLR_A::DISABLED
472    }
473    #[doc = "Enabled"]
474    #[inline(always)]
475    pub fn is_enabled(&self) -> bool {
476        *self == CMD_DAT_RX_PHASE_CLR_A::ENABLED
477    }
478}
479#[doc = "Field `cmd_dat_rx_phase_clr` writer - Clear the input phase of command lines and data lines during the update clock operation"]
480pub type CMD_DAT_RX_PHASE_CLR_W<'a, REG> = crate::BitWriter<'a, REG, CMD_DAT_RX_PHASE_CLR_A>;
481impl<'a, REG> CMD_DAT_RX_PHASE_CLR_W<'a, REG>
482where
483    REG: crate::Writable + crate::RegisterSpec,
484{
485    #[doc = "Disabled"]
486    #[inline(always)]
487    pub fn disabled(self) -> &'a mut crate::W<REG> {
488        self.variant(CMD_DAT_RX_PHASE_CLR_A::DISABLED)
489    }
490    #[doc = "Enabled"]
491    #[inline(always)]
492    pub fn enabled(self) -> &'a mut crate::W<REG> {
493        self.variant(CMD_DAT_RX_PHASE_CLR_A::ENABLED)
494    }
495}
496#[doc = "Field `mode_select` reader - "]
497pub type MODE_SELECT_R = crate::BitReader<MODE_SELECT_A>;
498#[doc = "\n\nValue on reset: 0"]
499#[derive(Clone, Copy, Debug, PartialEq, Eq)]
500pub enum MODE_SELECT_A {
501    #[doc = "0: Old mode of Sample/Output Timing"]
502    OLD_MODE = 0,
503    #[doc = "1: New mode of Sample/Output Timing"]
504    NEW_MODE = 1,
505}
506impl From<MODE_SELECT_A> for bool {
507    #[inline(always)]
508    fn from(variant: MODE_SELECT_A) -> Self {
509        variant as u8 != 0
510    }
511}
512impl MODE_SELECT_R {
513    #[doc = "Get enumerated values variant"]
514    #[inline(always)]
515    pub const fn variant(&self) -> MODE_SELECT_A {
516        match self.bits {
517            false => MODE_SELECT_A::OLD_MODE,
518            true => MODE_SELECT_A::NEW_MODE,
519        }
520    }
521    #[doc = "Old mode of Sample/Output Timing"]
522    #[inline(always)]
523    pub fn is_old_mode(&self) -> bool {
524        *self == MODE_SELECT_A::OLD_MODE
525    }
526    #[doc = "New mode of Sample/Output Timing"]
527    #[inline(always)]
528    pub fn is_new_mode(&self) -> bool {
529        *self == MODE_SELECT_A::NEW_MODE
530    }
531}
532#[doc = "Field `mode_select` writer - "]
533pub type MODE_SELECT_W<'a, REG> = crate::BitWriter<'a, REG, MODE_SELECT_A>;
534impl<'a, REG> MODE_SELECT_W<'a, REG>
535where
536    REG: crate::Writable + crate::RegisterSpec,
537{
538    #[doc = "Old mode of Sample/Output Timing"]
539    #[inline(always)]
540    pub fn old_mode(self) -> &'a mut crate::W<REG> {
541        self.variant(MODE_SELECT_A::OLD_MODE)
542    }
543    #[doc = "New mode of Sample/Output Timing"]
544    #[inline(always)]
545    pub fn new_mode(self) -> &'a mut crate::W<REG> {
546        self.variant(MODE_SELECT_A::NEW_MODE)
547    }
548}
549impl R {
550    #[doc = "Bit 0"]
551    #[inline(always)]
552    pub fn hs400_new_sample_en(&self) -> HS400_NEW_SAMPLE_EN_R {
553        HS400_NEW_SAMPLE_EN_R::new((self.bits & 1) != 0)
554    }
555    #[doc = "Bits 4:5"]
556    #[inline(always)]
557    pub fn cmd_sample_timing_phase(&self) -> CMD_SAMPLE_TIMING_PHASE_R {
558        CMD_SAMPLE_TIMING_PHASE_R::new(((self.bits >> 4) & 3) as u8)
559    }
560    #[doc = "Bits 8:9"]
561    #[inline(always)]
562    pub fn dat_sample_timing_phase(&self) -> DAT_SAMPLE_TIMING_PHASE_R {
563        DAT_SAMPLE_TIMING_PHASE_R::new(((self.bits >> 8) & 3) as u8)
564    }
565    #[doc = "Bit 16 - Clear command rx phase before sending the command"]
566    #[inline(always)]
567    pub fn cmd_send_rx_phase_clr(&self) -> CMD_SEND_RX_PHASE_CLR_R {
568        CMD_SEND_RX_PHASE_CLR_R::new(((self.bits >> 16) & 1) != 0)
569    }
570    #[doc = "Bit 20 - Clear the input phase of data lines before receiving the data"]
571    #[inline(always)]
572    pub fn dat_recv_rx_phase_clr(&self) -> DAT_RECV_RX_PHASE_CLR_R {
573        DAT_RECV_RX_PHASE_CLR_R::new(((self.bits >> 20) & 1) != 0)
574    }
575    #[doc = "Bit 21 - Clear the input phase of data lines before transferring the data"]
576    #[inline(always)]
577    pub fn dat_trans_rx_phase_clr(&self) -> DAT_TRANS_RX_PHASE_CLR_R {
578        DAT_TRANS_RX_PHASE_CLR_R::new(((self.bits >> 21) & 1) != 0)
579    }
580    #[doc = "Bit 22 - Clear the input phase of data lines before receiving the CRC status"]
581    #[inline(always)]
582    pub fn dat_crc_status_rx_phase_clr(&self) -> DAT_CRC_STATUS_RX_PHASE_CLR_R {
583        DAT_CRC_STATUS_RX_PHASE_CLR_R::new(((self.bits >> 22) & 1) != 0)
584    }
585    #[doc = "Bit 24 - Clear the input phase of command lines and data lines during the update clock operation"]
586    #[inline(always)]
587    pub fn cmd_dat_rx_phase_clr(&self) -> CMD_DAT_RX_PHASE_CLR_R {
588        CMD_DAT_RX_PHASE_CLR_R::new(((self.bits >> 24) & 1) != 0)
589    }
590    #[doc = "Bit 31"]
591    #[inline(always)]
592    pub fn mode_select(&self) -> MODE_SELECT_R {
593        MODE_SELECT_R::new(((self.bits >> 31) & 1) != 0)
594    }
595}
596impl W {
597    #[doc = "Bit 0"]
598    #[inline(always)]
599    #[must_use]
600    pub fn hs400_new_sample_en(&mut self) -> HS400_NEW_SAMPLE_EN_W<SMHC_NTSR_SPEC> {
601        HS400_NEW_SAMPLE_EN_W::new(self, 0)
602    }
603    #[doc = "Bits 4:5"]
604    #[inline(always)]
605    #[must_use]
606    pub fn cmd_sample_timing_phase(&mut self) -> CMD_SAMPLE_TIMING_PHASE_W<SMHC_NTSR_SPEC> {
607        CMD_SAMPLE_TIMING_PHASE_W::new(self, 4)
608    }
609    #[doc = "Bits 8:9"]
610    #[inline(always)]
611    #[must_use]
612    pub fn dat_sample_timing_phase(&mut self) -> DAT_SAMPLE_TIMING_PHASE_W<SMHC_NTSR_SPEC> {
613        DAT_SAMPLE_TIMING_PHASE_W::new(self, 8)
614    }
615    #[doc = "Bit 16 - Clear command rx phase before sending the command"]
616    #[inline(always)]
617    #[must_use]
618    pub fn cmd_send_rx_phase_clr(&mut self) -> CMD_SEND_RX_PHASE_CLR_W<SMHC_NTSR_SPEC> {
619        CMD_SEND_RX_PHASE_CLR_W::new(self, 16)
620    }
621    #[doc = "Bit 20 - Clear the input phase of data lines before receiving the data"]
622    #[inline(always)]
623    #[must_use]
624    pub fn dat_recv_rx_phase_clr(&mut self) -> DAT_RECV_RX_PHASE_CLR_W<SMHC_NTSR_SPEC> {
625        DAT_RECV_RX_PHASE_CLR_W::new(self, 20)
626    }
627    #[doc = "Bit 21 - Clear the input phase of data lines before transferring the data"]
628    #[inline(always)]
629    #[must_use]
630    pub fn dat_trans_rx_phase_clr(&mut self) -> DAT_TRANS_RX_PHASE_CLR_W<SMHC_NTSR_SPEC> {
631        DAT_TRANS_RX_PHASE_CLR_W::new(self, 21)
632    }
633    #[doc = "Bit 22 - Clear the input phase of data lines before receiving the CRC status"]
634    #[inline(always)]
635    #[must_use]
636    pub fn dat_crc_status_rx_phase_clr(&mut self) -> DAT_CRC_STATUS_RX_PHASE_CLR_W<SMHC_NTSR_SPEC> {
637        DAT_CRC_STATUS_RX_PHASE_CLR_W::new(self, 22)
638    }
639    #[doc = "Bit 24 - Clear the input phase of command lines and data lines during the update clock operation"]
640    #[inline(always)]
641    #[must_use]
642    pub fn cmd_dat_rx_phase_clr(&mut self) -> CMD_DAT_RX_PHASE_CLR_W<SMHC_NTSR_SPEC> {
643        CMD_DAT_RX_PHASE_CLR_W::new(self, 24)
644    }
645    #[doc = "Bit 31"]
646    #[inline(always)]
647    #[must_use]
648    pub fn mode_select(&mut self) -> MODE_SELECT_W<SMHC_NTSR_SPEC> {
649        MODE_SELECT_W::new(self, 31)
650    }
651    #[doc = r" Writes raw bits to the register."]
652    #[doc = r""]
653    #[doc = r" # Safety"]
654    #[doc = r""]
655    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
656    #[inline(always)]
657    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
658        self.bits = bits;
659        self
660    }
661}
662#[doc = "SD New Timing Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_ntsr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_ntsr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
663pub struct SMHC_NTSR_SPEC;
664impl crate::RegisterSpec for SMHC_NTSR_SPEC {
665    type Ux = u32;
666}
667#[doc = "`read()` method returns [`smhc_ntsr::R`](R) reader structure"]
668impl crate::Readable for SMHC_NTSR_SPEC {}
669#[doc = "`write(|w| ..)` method takes [`smhc_ntsr::W`](W) writer structure"]
670impl crate::Writable for SMHC_NTSR_SPEC {
671    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
672    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
673}
674#[doc = "`reset()` method sets smhc_ntsr to value 0"]
675impl crate::Resettable for SMHC_NTSR_SPEC {
676    const RESET_VALUE: Self::Ux = 0;
677}
d1_pac/smhc/smhc_ntsr.rs

d1_pac/smhc/
smhc_ntsr.rs
