d1_pac/smhc/
smhc_mintsts.rs

1#[doc = "Register `smhc_mintsts` reader"]
2pub type R = crate::R<SMHC_MINTSTS_SPEC>;
3#[doc = "Field `m_re_int` reader - Response Errors"]
4pub type M_RE_INT_R = crate::BitReader;
5#[doc = "Field `m_cc_int` reader - Command Complete"]
6pub type M_CC_INT_R = crate::BitReader;
7#[doc = "Field `m_dtc_int` reader - Data Transfer Complete"]
8pub type M_DTC_INT_R = crate::BitReader;
9#[doc = "Field `m_dtr_int` reader - Data Transmit Request"]
10pub type M_DTR_INT_R = crate::BitReader;
11#[doc = "Field `m_drr_int` reader - Data Receive Request"]
12pub type M_DRR_INT_R = crate::BitReader;
13#[doc = "Field `m_rce_int` reader - Response CRC Error"]
14pub type M_RCE_INT_R = crate::BitReader;
15#[doc = "Field `m_dce_int` reader - Data CRC Error"]
16pub type M_DCE_INT_R = crate::BitReader;
17#[doc = "Field `m_rto_back_int` reader - Response Timeout/Boot ACK Received"]
18pub type M_RTO_BACK_INT_R = crate::BitReader;
19#[doc = "Field `m_dto_bds_int` reader - Data Timeout/Boot Data Start"]
20pub type M_DTO_BDS_INT_R = crate::BitReader;
21#[doc = "Field `m_dsto_vsd_int` reader - Data Starvation Timeout/V1.8 Switch Done"]
22pub type M_DSTO_VSD_INT_R = crate::BitReader;
23#[doc = "Field `m_fu_fo_int` reader - FIFO Underrun/Overflow"]
24pub type M_FU_FO_INT_R = crate::BitReader;
25#[doc = "Field `m_cb_iw_int` reader - Command Busy and Illegal Write"]
26pub type M_CB_IW_INT_R = crate::BitReader;
27#[doc = "Field `m_dse_bc_int` reader - Data Start Error/Busy Clear"]
28pub type M_DSE_BC_INT_R = crate::BitReader;
29#[doc = "Field `m_acd_int` reader - Auto Command Done"]
30pub type M_ACD_INT_R = crate::BitReader;
31#[doc = "Field `m_dee_int` reader - Data End-bit Error"]
32pub type M_DEE_INT_R = crate::BitReader;
33#[doc = "Field `m_sdio_int` reader - SDIO Interrupt"]
34pub type M_SDIO_INT_R = crate::BitReader;
35#[doc = "Field `m_card_insert` reader - Card Inserted"]
36pub type M_CARD_INSERT_R = crate::BitReader;
37#[doc = "Field `m_card_removal_int` reader - Card Removed"]
38pub type M_CARD_REMOVAL_INT_R = crate::BitReader;
39impl R {
40    #[doc = "Bit 1 - Response Errors"]
41    #[inline(always)]
42    pub fn m_re_int(&self) -> M_RE_INT_R {
43        M_RE_INT_R::new(((self.bits >> 1) & 1) != 0)
44    }
45    #[doc = "Bit 2 - Command Complete"]
46    #[inline(always)]
47    pub fn m_cc_int(&self) -> M_CC_INT_R {
48        M_CC_INT_R::new(((self.bits >> 2) & 1) != 0)
49    }
50    #[doc = "Bit 3 - Data Transfer Complete"]
51    #[inline(always)]
52    pub fn m_dtc_int(&self) -> M_DTC_INT_R {
53        M_DTC_INT_R::new(((self.bits >> 3) & 1) != 0)
54    }
55    #[doc = "Bit 4 - Data Transmit Request"]
56    #[inline(always)]
57    pub fn m_dtr_int(&self) -> M_DTR_INT_R {
58        M_DTR_INT_R::new(((self.bits >> 4) & 1) != 0)
59    }
60    #[doc = "Bit 5 - Data Receive Request"]
61    #[inline(always)]
62    pub fn m_drr_int(&self) -> M_DRR_INT_R {
63        M_DRR_INT_R::new(((self.bits >> 5) & 1) != 0)
64    }
65    #[doc = "Bit 6 - Response CRC Error"]
66    #[inline(always)]
67    pub fn m_rce_int(&self) -> M_RCE_INT_R {
68        M_RCE_INT_R::new(((self.bits >> 6) & 1) != 0)
69    }
70    #[doc = "Bit 7 - Data CRC Error"]
71    #[inline(always)]
72    pub fn m_dce_int(&self) -> M_DCE_INT_R {
73        M_DCE_INT_R::new(((self.bits >> 7) & 1) != 0)
74    }
75    #[doc = "Bit 8 - Response Timeout/Boot ACK Received"]
76    #[inline(always)]
77    pub fn m_rto_back_int(&self) -> M_RTO_BACK_INT_R {
78        M_RTO_BACK_INT_R::new(((self.bits >> 8) & 1) != 0)
79    }
80    #[doc = "Bit 9 - Data Timeout/Boot Data Start"]
81    #[inline(always)]
82    pub fn m_dto_bds_int(&self) -> M_DTO_BDS_INT_R {
83        M_DTO_BDS_INT_R::new(((self.bits >> 9) & 1) != 0)
84    }
85    #[doc = "Bit 10 - Data Starvation Timeout/V1.8 Switch Done"]
86    #[inline(always)]
87    pub fn m_dsto_vsd_int(&self) -> M_DSTO_VSD_INT_R {
88        M_DSTO_VSD_INT_R::new(((self.bits >> 10) & 1) != 0)
89    }
90    #[doc = "Bit 11 - FIFO Underrun/Overflow"]
91    #[inline(always)]
92    pub fn m_fu_fo_int(&self) -> M_FU_FO_INT_R {
93        M_FU_FO_INT_R::new(((self.bits >> 11) & 1) != 0)
94    }
95    #[doc = "Bit 12 - Command Busy and Illegal Write"]
96    #[inline(always)]
97    pub fn m_cb_iw_int(&self) -> M_CB_IW_INT_R {
98        M_CB_IW_INT_R::new(((self.bits >> 12) & 1) != 0)
99    }
100    #[doc = "Bit 13 - Data Start Error/Busy Clear"]
101    #[inline(always)]
102    pub fn m_dse_bc_int(&self) -> M_DSE_BC_INT_R {
103        M_DSE_BC_INT_R::new(((self.bits >> 13) & 1) != 0)
104    }
105    #[doc = "Bit 14 - Auto Command Done"]
106    #[inline(always)]
107    pub fn m_acd_int(&self) -> M_ACD_INT_R {
108        M_ACD_INT_R::new(((self.bits >> 14) & 1) != 0)
109    }
110    #[doc = "Bit 15 - Data End-bit Error"]
111    #[inline(always)]
112    pub fn m_dee_int(&self) -> M_DEE_INT_R {
113        M_DEE_INT_R::new(((self.bits >> 15) & 1) != 0)
114    }
115    #[doc = "Bit 16 - SDIO Interrupt"]
116    #[inline(always)]
117    pub fn m_sdio_int(&self) -> M_SDIO_INT_R {
118        M_SDIO_INT_R::new(((self.bits >> 16) & 1) != 0)
119    }
120    #[doc = "Bit 30 - Card Inserted"]
121    #[inline(always)]
122    pub fn m_card_insert(&self) -> M_CARD_INSERT_R {
123        M_CARD_INSERT_R::new(((self.bits >> 30) & 1) != 0)
124    }
125    #[doc = "Bit 31 - Card Removed"]
126    #[inline(always)]
127    pub fn m_card_removal_int(&self) -> M_CARD_REMOVAL_INT_R {
128        M_CARD_REMOVAL_INT_R::new(((self.bits >> 31) & 1) != 0)
129    }
130}
131#[doc = "Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_mintsts::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
132pub struct SMHC_MINTSTS_SPEC;
133impl crate::RegisterSpec for SMHC_MINTSTS_SPEC {
134    type Ux = u32;
135}
136#[doc = "`read()` method returns [`smhc_mintsts::R`](R) reader structure"]
137impl crate::Readable for SMHC_MINTSTS_SPEC {}
138#[doc = "`reset()` method sets smhc_mintsts to value 0"]
139impl crate::Resettable for SMHC_MINTSTS_SPEC {
140    const RESET_VALUE: Self::Ux = 0;
141}
d1_pac/smhc/smhc_mintsts.rs

d1_pac/smhc/
smhc_mintsts.rs
