d1_pac/smhc/
smhc_idst.rs

1#[doc = "Register `smhc_idst` reader"]
2pub type R = crate::R<SMHC_IDST_SPEC>;
3#[doc = "Register `smhc_idst` writer"]
4pub type W = crate::W<SMHC_IDST_SPEC>;
5#[doc = "Field `tx_int` reader - Transmit Interrupt"]
6pub type TX_INT_R = crate::BitReader;
7#[doc = "Field `tx_int` writer - Transmit Interrupt"]
8pub type TX_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `rx_int` reader - Receive Interrupt"]
10pub type RX_INT_R = crate::BitReader;
11#[doc = "Field `rx_int` writer - Receive Interrupt"]
12pub type RX_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `fatal_berr_int` reader - Fatal Bus Error Interrupt"]
14pub type FATAL_BERR_INT_R = crate::BitReader;
15#[doc = "Field `fatal_berr_int` writer - Fatal Bus Error Interrupt"]
16pub type FATAL_BERR_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `des_unavl_int` reader - Descriptor Unavailable Interrupt"]
18pub type DES_UNAVL_INT_R = crate::BitReader;
19#[doc = "Field `des_unavl_int` writer - Descriptor Unavailable Interrupt"]
20pub type DES_UNAVL_INT_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `err_flag_sum` reader - Card Error Summary"]
22pub type ERR_FLAG_SUM_R = crate::BitReader;
23#[doc = "Field `err_flag_sum` writer - Card Error Summary"]
24pub type ERR_FLAG_SUM_W<'a, REG> = crate::BitWriter<'a, REG>;
25#[doc = "Field `nor_int_sum` reader - Normal Interrupt Summary"]
26pub type NOR_INT_SUM_R = crate::BitReader;
27#[doc = "Field `nor_int_sum` writer - Normal Interrupt Summary"]
28pub type NOR_INT_SUM_W<'a, REG> = crate::BitWriter<'a, REG>;
29#[doc = "Field `abn_int_sum` reader - Abnormal Interrupt Summary"]
30pub type ABN_INT_SUM_R = crate::BitReader;
31#[doc = "Field `abn_int_sum` writer - Abnormal Interrupt Summary"]
32pub type ABN_INT_SUM_W<'a, REG> = crate::BitWriter<'a, REG>;
33#[doc = "Field `idmac_err_sta` reader - Error Bits"]
34pub type IDMAC_ERR_STA_R = crate::FieldReader<IDMAC_ERR_STA_A>;
35#[doc = "Error Bits\n\nValue on reset: 0"]
36#[derive(Clone, Copy, Debug, PartialEq, Eq)]
37#[repr(u8)]
38pub enum IDMAC_ERR_STA_A {
39    #[doc = "1: Host Abort received during the transmission"]
40    TRANSMISSION = 1,
41    #[doc = "2: Host Abort received during the reception"]
42    RECEPTION = 2,
43}
44impl From<IDMAC_ERR_STA_A> for u8 {
45    #[inline(always)]
46    fn from(variant: IDMAC_ERR_STA_A) -> Self {
47        variant as _
48    }
49}
50impl crate::FieldSpec for IDMAC_ERR_STA_A {
51    type Ux = u8;
52}
53impl IDMAC_ERR_STA_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub const fn variant(&self) -> Option<IDMAC_ERR_STA_A> {
57        match self.bits {
58            1 => Some(IDMAC_ERR_STA_A::TRANSMISSION),
59            2 => Some(IDMAC_ERR_STA_A::RECEPTION),
60            _ => None,
61        }
62    }
63    #[doc = "Host Abort received during the transmission"]
64    #[inline(always)]
65    pub fn is_transmission(&self) -> bool {
66        *self == IDMAC_ERR_STA_A::TRANSMISSION
67    }
68    #[doc = "Host Abort received during the reception"]
69    #[inline(always)]
70    pub fn is_reception(&self) -> bool {
71        *self == IDMAC_ERR_STA_A::RECEPTION
72    }
73}
74impl R {
75    #[doc = "Bit 0 - Transmit Interrupt"]
76    #[inline(always)]
77    pub fn tx_int(&self) -> TX_INT_R {
78        TX_INT_R::new((self.bits & 1) != 0)
79    }
80    #[doc = "Bit 1 - Receive Interrupt"]
81    #[inline(always)]
82    pub fn rx_int(&self) -> RX_INT_R {
83        RX_INT_R::new(((self.bits >> 1) & 1) != 0)
84    }
85    #[doc = "Bit 2 - Fatal Bus Error Interrupt"]
86    #[inline(always)]
87    pub fn fatal_berr_int(&self) -> FATAL_BERR_INT_R {
88        FATAL_BERR_INT_R::new(((self.bits >> 2) & 1) != 0)
89    }
90    #[doc = "Bit 4 - Descriptor Unavailable Interrupt"]
91    #[inline(always)]
92    pub fn des_unavl_int(&self) -> DES_UNAVL_INT_R {
93        DES_UNAVL_INT_R::new(((self.bits >> 4) & 1) != 0)
94    }
95    #[doc = "Bit 5 - Card Error Summary"]
96    #[inline(always)]
97    pub fn err_flag_sum(&self) -> ERR_FLAG_SUM_R {
98        ERR_FLAG_SUM_R::new(((self.bits >> 5) & 1) != 0)
99    }
100    #[doc = "Bit 8 - Normal Interrupt Summary"]
101    #[inline(always)]
102    pub fn nor_int_sum(&self) -> NOR_INT_SUM_R {
103        NOR_INT_SUM_R::new(((self.bits >> 8) & 1) != 0)
104    }
105    #[doc = "Bit 9 - Abnormal Interrupt Summary"]
106    #[inline(always)]
107    pub fn abn_int_sum(&self) -> ABN_INT_SUM_R {
108        ABN_INT_SUM_R::new(((self.bits >> 9) & 1) != 0)
109    }
110    #[doc = "Bits 10:12 - Error Bits"]
111    #[inline(always)]
112    pub fn idmac_err_sta(&self) -> IDMAC_ERR_STA_R {
113        IDMAC_ERR_STA_R::new(((self.bits >> 10) & 7) as u8)
114    }
115}
116impl W {
117    #[doc = "Bit 0 - Transmit Interrupt"]
118    #[inline(always)]
119    #[must_use]
120    pub fn tx_int(&mut self) -> TX_INT_W<SMHC_IDST_SPEC> {
121        TX_INT_W::new(self, 0)
122    }
123    #[doc = "Bit 1 - Receive Interrupt"]
124    #[inline(always)]
125    #[must_use]
126    pub fn rx_int(&mut self) -> RX_INT_W<SMHC_IDST_SPEC> {
127        RX_INT_W::new(self, 1)
128    }
129    #[doc = "Bit 2 - Fatal Bus Error Interrupt"]
130    #[inline(always)]
131    #[must_use]
132    pub fn fatal_berr_int(&mut self) -> FATAL_BERR_INT_W<SMHC_IDST_SPEC> {
133        FATAL_BERR_INT_W::new(self, 2)
134    }
135    #[doc = "Bit 4 - Descriptor Unavailable Interrupt"]
136    #[inline(always)]
137    #[must_use]
138    pub fn des_unavl_int(&mut self) -> DES_UNAVL_INT_W<SMHC_IDST_SPEC> {
139        DES_UNAVL_INT_W::new(self, 4)
140    }
141    #[doc = "Bit 5 - Card Error Summary"]
142    #[inline(always)]
143    #[must_use]
144    pub fn err_flag_sum(&mut self) -> ERR_FLAG_SUM_W<SMHC_IDST_SPEC> {
145        ERR_FLAG_SUM_W::new(self, 5)
146    }
147    #[doc = "Bit 8 - Normal Interrupt Summary"]
148    #[inline(always)]
149    #[must_use]
150    pub fn nor_int_sum(&mut self) -> NOR_INT_SUM_W<SMHC_IDST_SPEC> {
151        NOR_INT_SUM_W::new(self, 8)
152    }
153    #[doc = "Bit 9 - Abnormal Interrupt Summary"]
154    #[inline(always)]
155    #[must_use]
156    pub fn abn_int_sum(&mut self) -> ABN_INT_SUM_W<SMHC_IDST_SPEC> {
157        ABN_INT_SUM_W::new(self, 9)
158    }
159    #[doc = r" Writes raw bits to the register."]
160    #[doc = r""]
161    #[doc = r" # Safety"]
162    #[doc = r""]
163    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
164    #[inline(always)]
165    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
166        self.bits = bits;
167        self
168    }
169}
170#[doc = "IDMAC Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_idst::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_idst::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
171pub struct SMHC_IDST_SPEC;
172impl crate::RegisterSpec for SMHC_IDST_SPEC {
173    type Ux = u32;
174}
175#[doc = "`read()` method returns [`smhc_idst::R`](R) reader structure"]
176impl crate::Readable for SMHC_IDST_SPEC {}
177#[doc = "`write(|w| ..)` method takes [`smhc_idst::W`](W) writer structure"]
178impl crate::Writable for SMHC_IDST_SPEC {
179    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
180    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
181}
182#[doc = "`reset()` method sets smhc_idst to value 0"]
183impl crate::Resettable for SMHC_IDST_SPEC {
184    const RESET_VALUE: Self::Ux = 0;
185}
d1_pac/smhc/smhc_idst.rs

d1_pac/smhc/
smhc_idst.rs
