d1_pac/smhc/
smhc_idmac.rs

1#[doc = "Register `smhc_idmac` reader"]
2pub type R = crate::R<SMHC_IDMAC_SPEC>;
3#[doc = "Register `smhc_idmac` writer"]
4pub type W = crate::W<SMHC_IDMAC_SPEC>;
5#[doc = "Field `idmac_rst` reader - DMA Reset"]
6pub type IDMAC_RST_R = crate::BitReader;
7#[doc = "Field `idmac_rst` writer - DMA Reset"]
8pub type IDMAC_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `fix_bust_ctrl` reader - Fixed Burst"]
10pub type FIX_BUST_CTRL_R = crate::BitReader;
11#[doc = "Field `fix_bust_ctrl` writer - Fixed Burst"]
12pub type FIX_BUST_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `idmac_enb` reader - IDMAC Enable"]
14pub type IDMAC_ENB_R = crate::BitReader;
15#[doc = "Field `idmac_enb` writer - IDMAC Enable"]
16pub type IDMAC_ENB_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `des_load_ctrl` writer - "]
18pub type DES_LOAD_CTRL_W<'a, REG> = crate::BitWriter<'a, REG>;
19impl R {
20    #[doc = "Bit 0 - DMA Reset"]
21    #[inline(always)]
22    pub fn idmac_rst(&self) -> IDMAC_RST_R {
23        IDMAC_RST_R::new((self.bits & 1) != 0)
24    }
25    #[doc = "Bit 1 - Fixed Burst"]
26    #[inline(always)]
27    pub fn fix_bust_ctrl(&self) -> FIX_BUST_CTRL_R {
28        FIX_BUST_CTRL_R::new(((self.bits >> 1) & 1) != 0)
29    }
30    #[doc = "Bit 7 - IDMAC Enable"]
31    #[inline(always)]
32    pub fn idmac_enb(&self) -> IDMAC_ENB_R {
33        IDMAC_ENB_R::new(((self.bits >> 7) & 1) != 0)
34    }
35}
36impl W {
37    #[doc = "Bit 0 - DMA Reset"]
38    #[inline(always)]
39    #[must_use]
40    pub fn idmac_rst(&mut self) -> IDMAC_RST_W<SMHC_IDMAC_SPEC> {
41        IDMAC_RST_W::new(self, 0)
42    }
43    #[doc = "Bit 1 - Fixed Burst"]
44    #[inline(always)]
45    #[must_use]
46    pub fn fix_bust_ctrl(&mut self) -> FIX_BUST_CTRL_W<SMHC_IDMAC_SPEC> {
47        FIX_BUST_CTRL_W::new(self, 1)
48    }
49    #[doc = "Bit 7 - IDMAC Enable"]
50    #[inline(always)]
51    #[must_use]
52    pub fn idmac_enb(&mut self) -> IDMAC_ENB_W<SMHC_IDMAC_SPEC> {
53        IDMAC_ENB_W::new(self, 7)
54    }
55    #[doc = "Bit 31"]
56    #[inline(always)]
57    #[must_use]
58    pub fn des_load_ctrl(&mut self) -> DES_LOAD_CTRL_W<SMHC_IDMAC_SPEC> {
59        DES_LOAD_CTRL_W::new(self, 31)
60    }
61    #[doc = r" Writes raw bits to the register."]
62    #[doc = r""]
63    #[doc = r" # Safety"]
64    #[doc = r""]
65    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
66    #[inline(always)]
67    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
68        self.bits = bits;
69        self
70    }
71}
72#[doc = "IDMAC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_idmac::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_idmac::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
73pub struct SMHC_IDMAC_SPEC;
74impl crate::RegisterSpec for SMHC_IDMAC_SPEC {
75    type Ux = u32;
76}
77#[doc = "`read()` method returns [`smhc_idmac::R`](R) reader structure"]
78impl crate::Readable for SMHC_IDMAC_SPEC {}
79#[doc = "`write(|w| ..)` method takes [`smhc_idmac::W`](W) writer structure"]
80impl crate::Writable for SMHC_IDMAC_SPEC {
81    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
82    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
83}
84#[doc = "`reset()` method sets smhc_idmac to value 0"]
85impl crate::Resettable for SMHC_IDMAC_SPEC {
86    const RESET_VALUE: Self::Ux = 0;
87}
d1_pac/smhc/smhc_idmac.rs

d1_pac/smhc/
smhc_idmac.rs
