d1_pac/smhc/
smhc_idie.rs

1#[doc = "Register `smhc_idie` reader"]
2pub type R = crate::R<SMHC_IDIE_SPEC>;
3#[doc = "Register `smhc_idie` writer"]
4pub type W = crate::W<SMHC_IDIE_SPEC>;
5#[doc = "Field `tx_int_enb` reader - Transmit Interrupt Enable"]
6pub type TX_INT_ENB_R = crate::BitReader;
7#[doc = "Field `tx_int_enb` writer - Transmit Interrupt Enable"]
8pub type TX_INT_ENB_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `rx_int_enb` reader - Receive Interrupt Enables"]
10pub type RX_INT_ENB_R = crate::BitReader;
11#[doc = "Field `rx_int_enb` writer - Receive Interrupt Enables"]
12pub type RX_INT_ENB_W<'a, REG> = crate::BitWriter<'a, REG>;
13#[doc = "Field `ferr_int_enb` reader - Fatal Bus Error Enable"]
14pub type FERR_INT_ENB_R = crate::BitReader;
15#[doc = "Field `ferr_int_enb` writer - Fatal Bus Error Enable"]
16pub type FERR_INT_ENB_W<'a, REG> = crate::BitWriter<'a, REG>;
17#[doc = "Field `des_unavl_int_enb` reader - Descriptor Unavailable Interrupt"]
18pub type DES_UNAVL_INT_ENB_R = crate::BitReader;
19#[doc = "Field `des_unavl_int_enb` writer - Descriptor Unavailable Interrupt"]
20pub type DES_UNAVL_INT_ENB_W<'a, REG> = crate::BitWriter<'a, REG>;
21#[doc = "Field `err_sum_int_enb` reader - Card Error Summary Interrupt Enable"]
22pub type ERR_SUM_INT_ENB_R = crate::BitReader;
23#[doc = "Field `err_sum_int_enb` writer - Card Error Summary Interrupt Enable"]
24pub type ERR_SUM_INT_ENB_W<'a, REG> = crate::BitWriter<'a, REG>;
25impl R {
26    #[doc = "Bit 0 - Transmit Interrupt Enable"]
27    #[inline(always)]
28    pub fn tx_int_enb(&self) -> TX_INT_ENB_R {
29        TX_INT_ENB_R::new((self.bits & 1) != 0)
30    }
31    #[doc = "Bit 1 - Receive Interrupt Enables"]
32    #[inline(always)]
33    pub fn rx_int_enb(&self) -> RX_INT_ENB_R {
34        RX_INT_ENB_R::new(((self.bits >> 1) & 1) != 0)
35    }
36    #[doc = "Bit 2 - Fatal Bus Error Enable"]
37    #[inline(always)]
38    pub fn ferr_int_enb(&self) -> FERR_INT_ENB_R {
39        FERR_INT_ENB_R::new(((self.bits >> 2) & 1) != 0)
40    }
41    #[doc = "Bit 4 - Descriptor Unavailable Interrupt"]
42    #[inline(always)]
43    pub fn des_unavl_int_enb(&self) -> DES_UNAVL_INT_ENB_R {
44        DES_UNAVL_INT_ENB_R::new(((self.bits >> 4) & 1) != 0)
45    }
46    #[doc = "Bit 5 - Card Error Summary Interrupt Enable"]
47    #[inline(always)]
48    pub fn err_sum_int_enb(&self) -> ERR_SUM_INT_ENB_R {
49        ERR_SUM_INT_ENB_R::new(((self.bits >> 5) & 1) != 0)
50    }
51}
52impl W {
53    #[doc = "Bit 0 - Transmit Interrupt Enable"]
54    #[inline(always)]
55    #[must_use]
56    pub fn tx_int_enb(&mut self) -> TX_INT_ENB_W<SMHC_IDIE_SPEC> {
57        TX_INT_ENB_W::new(self, 0)
58    }
59    #[doc = "Bit 1 - Receive Interrupt Enables"]
60    #[inline(always)]
61    #[must_use]
62    pub fn rx_int_enb(&mut self) -> RX_INT_ENB_W<SMHC_IDIE_SPEC> {
63        RX_INT_ENB_W::new(self, 1)
64    }
65    #[doc = "Bit 2 - Fatal Bus Error Enable"]
66    #[inline(always)]
67    #[must_use]
68    pub fn ferr_int_enb(&mut self) -> FERR_INT_ENB_W<SMHC_IDIE_SPEC> {
69        FERR_INT_ENB_W::new(self, 2)
70    }
71    #[doc = "Bit 4 - Descriptor Unavailable Interrupt"]
72    #[inline(always)]
73    #[must_use]
74    pub fn des_unavl_int_enb(&mut self) -> DES_UNAVL_INT_ENB_W<SMHC_IDIE_SPEC> {
75        DES_UNAVL_INT_ENB_W::new(self, 4)
76    }
77    #[doc = "Bit 5 - Card Error Summary Interrupt Enable"]
78    #[inline(always)]
79    #[must_use]
80    pub fn err_sum_int_enb(&mut self) -> ERR_SUM_INT_ENB_W<SMHC_IDIE_SPEC> {
81        ERR_SUM_INT_ENB_W::new(self, 5)
82    }
83    #[doc = r" Writes raw bits to the register."]
84    #[doc = r""]
85    #[doc = r" # Safety"]
86    #[doc = r""]
87    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
88    #[inline(always)]
89    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
90        self.bits = bits;
91        self
92    }
93}
94#[doc = "IDMAC Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_idie::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_idie::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
95pub struct SMHC_IDIE_SPEC;
96impl crate::RegisterSpec for SMHC_IDIE_SPEC {
97    type Ux = u32;
98}
99#[doc = "`read()` method returns [`smhc_idie::R`](R) reader structure"]
100impl crate::Readable for SMHC_IDIE_SPEC {}
101#[doc = "`write(|w| ..)` method takes [`smhc_idie::W`](W) writer structure"]
102impl crate::Writable for SMHC_IDIE_SPEC {
103    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
104    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
105}
106#[doc = "`reset()` method sets smhc_idie to value 0"]
107impl crate::Resettable for SMHC_IDIE_SPEC {
108    const RESET_VALUE: Self::Ux = 0;
109}
d1_pac/smhc/smhc_idie.rs

d1_pac/smhc/
smhc_idie.rs
