d1_pac/smhc/
smhc_drv_dl.rs

1#[doc = "Register `smhc_drv_dl` reader"]
2pub type R = crate::R<SMHC_DRV_DL_SPEC>;
3#[doc = "Register `smhc_drv_dl` writer"]
4pub type W = crate::W<SMHC_DRV_DL_SPEC>;
5#[doc = "Field `cmd_drv_ph_sel` reader - Command Drive Phase Select"]
6pub type CMD_DRV_PH_SEL_R = crate::BitReader;
7#[doc = "Field `cmd_drv_ph_sel` writer - Command Drive Phase Select"]
8pub type CMD_DRV_PH_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
9#[doc = "Field `dat_drv_ph_sel` reader - Data Drive Phase Select"]
10pub type DAT_DRV_PH_SEL_R = crate::BitReader;
11#[doc = "Field `dat_drv_ph_sel` writer - Data Drive Phase Select"]
12pub type DAT_DRV_PH_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
13impl R {
14    #[doc = "Bit 16 - Command Drive Phase Select"]
15    #[inline(always)]
16    pub fn cmd_drv_ph_sel(&self) -> CMD_DRV_PH_SEL_R {
17        CMD_DRV_PH_SEL_R::new(((self.bits >> 16) & 1) != 0)
18    }
19    #[doc = "Bit 17 - Data Drive Phase Select"]
20    #[inline(always)]
21    pub fn dat_drv_ph_sel(&self) -> DAT_DRV_PH_SEL_R {
22        DAT_DRV_PH_SEL_R::new(((self.bits >> 17) & 1) != 0)
23    }
24}
25impl W {
26    #[doc = "Bit 16 - Command Drive Phase Select"]
27    #[inline(always)]
28    #[must_use]
29    pub fn cmd_drv_ph_sel(&mut self) -> CMD_DRV_PH_SEL_W<SMHC_DRV_DL_SPEC> {
30        CMD_DRV_PH_SEL_W::new(self, 16)
31    }
32    #[doc = "Bit 17 - Data Drive Phase Select"]
33    #[inline(always)]
34    #[must_use]
35    pub fn dat_drv_ph_sel(&mut self) -> DAT_DRV_PH_SEL_W<SMHC_DRV_DL_SPEC> {
36        DAT_DRV_PH_SEL_W::new(self, 17)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "Drive Delay Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_drv_dl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_drv_dl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct SMHC_DRV_DL_SPEC;
51impl crate::RegisterSpec for SMHC_DRV_DL_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`smhc_drv_dl::R`](R) reader structure"]
55impl crate::Readable for SMHC_DRV_DL_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`smhc_drv_dl::W`](W) writer structure"]
57impl crate::Writable for SMHC_DRV_DL_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets smhc_drv_dl to value 0"]
62impl crate::Resettable for SMHC_DRV_DL_SPEC {
63    const RESET_VALUE: Self::Ux = 0;
64}
d1_pac/smhc/smhc_drv_dl.rs

d1_pac/smhc/
smhc_drv_dl.rs
