d1_pac/smhc/
smhc_ctrl.rs

1#[doc = "Register `smhc_ctrl` reader"]
2pub type R = crate::R<SMHC_CTRL_SPEC>;
3#[doc = "Register `smhc_ctrl` writer"]
4pub type W = crate::W<SMHC_CTRL_SPEC>;
5#[doc = "Field `soft_rst` reader - Software Reset"]
6pub type SOFT_RST_R = crate::BitReader<SOFT_RST_A>;
7#[doc = "Software Reset\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum SOFT_RST_A {
10    #[doc = "0: `0`"]
11    NO_EFFECT = 0,
12    #[doc = "1: `1`"]
13    RESET = 1,
14}
15impl From<SOFT_RST_A> for bool {
16    #[inline(always)]
17    fn from(variant: SOFT_RST_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl SOFT_RST_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> SOFT_RST_A {
25        match self.bits {
26            false => SOFT_RST_A::NO_EFFECT,
27            true => SOFT_RST_A::RESET,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_no_effect(&self) -> bool {
33        *self == SOFT_RST_A::NO_EFFECT
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_reset(&self) -> bool {
38        *self == SOFT_RST_A::RESET
39    }
40}
41#[doc = "Field `soft_rst` writer - Software Reset"]
42pub type SOFT_RST_W<'a, REG> = crate::BitWriter<'a, REG, SOFT_RST_A>;
43impl<'a, REG> SOFT_RST_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn no_effect(self) -> &'a mut crate::W<REG> {
50        self.variant(SOFT_RST_A::NO_EFFECT)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn reset(self) -> &'a mut crate::W<REG> {
55        self.variant(SOFT_RST_A::RESET)
56    }
57}
58#[doc = "Field `fifo_rst` reader - FIFO Reset"]
59pub type FIFO_RST_R = crate::BitReader<FIFO_RST_A>;
60#[doc = "FIFO Reset\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum FIFO_RST_A {
63    #[doc = "0: `0`"]
64    NO_EFFECT = 0,
65    #[doc = "1: `1`"]
66    RESET = 1,
67}
68impl From<FIFO_RST_A> for bool {
69    #[inline(always)]
70    fn from(variant: FIFO_RST_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl FIFO_RST_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> FIFO_RST_A {
78        match self.bits {
79            false => FIFO_RST_A::NO_EFFECT,
80            true => FIFO_RST_A::RESET,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_no_effect(&self) -> bool {
86        *self == FIFO_RST_A::NO_EFFECT
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_reset(&self) -> bool {
91        *self == FIFO_RST_A::RESET
92    }
93}
94#[doc = "Field `fifo_rst` writer - FIFO Reset"]
95pub type FIFO_RST_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_RST_A>;
96impl<'a, REG> FIFO_RST_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn no_effect(self) -> &'a mut crate::W<REG> {
103        self.variant(FIFO_RST_A::NO_EFFECT)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn reset(self) -> &'a mut crate::W<REG> {
108        self.variant(FIFO_RST_A::RESET)
109    }
110}
111#[doc = "Field `dma_rst` reader - DMA Reset"]
112pub type DMA_RST_R = crate::BitReader;
113#[doc = "Field `dma_rst` writer - DMA Reset"]
114pub type DMA_RST_W<'a, REG> = crate::BitWriter<'a, REG>;
115#[doc = "Field `ine_enb` reader - GLobal Interrupt Enable"]
116pub type INE_ENB_R = crate::BitReader<INE_ENB_A>;
117#[doc = "GLobal Interrupt Enable\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119pub enum INE_ENB_A {
120    #[doc = "0: Disable interrupts"]
121    DISABLE = 0,
122    #[doc = "1: Enable interrupts"]
123    ENABLE = 1,
124}
125impl From<INE_ENB_A> for bool {
126    #[inline(always)]
127    fn from(variant: INE_ENB_A) -> Self {
128        variant as u8 != 0
129    }
130}
131impl INE_ENB_R {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub const fn variant(&self) -> INE_ENB_A {
135        match self.bits {
136            false => INE_ENB_A::DISABLE,
137            true => INE_ENB_A::ENABLE,
138        }
139    }
140    #[doc = "Disable interrupts"]
141    #[inline(always)]
142    pub fn is_disable(&self) -> bool {
143        *self == INE_ENB_A::DISABLE
144    }
145    #[doc = "Enable interrupts"]
146    #[inline(always)]
147    pub fn is_enable(&self) -> bool {
148        *self == INE_ENB_A::ENABLE
149    }
150}
151#[doc = "Field `ine_enb` writer - GLobal Interrupt Enable"]
152pub type INE_ENB_W<'a, REG> = crate::BitWriter<'a, REG, INE_ENB_A>;
153impl<'a, REG> INE_ENB_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156{
157    #[doc = "Disable interrupts"]
158    #[inline(always)]
159    pub fn disable(self) -> &'a mut crate::W<REG> {
160        self.variant(INE_ENB_A::DISABLE)
161    }
162    #[doc = "Enable interrupts"]
163    #[inline(always)]
164    pub fn enable(self) -> &'a mut crate::W<REG> {
165        self.variant(INE_ENB_A::ENABLE)
166    }
167}
168#[doc = "Field `dma_enb` reader - DMA Global Enable"]
169pub type DMA_ENB_R = crate::BitReader<DMA_ENB_A>;
170#[doc = "DMA Global Enable\n\nValue on reset: 0"]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172pub enum DMA_ENB_A {
173    #[doc = "0: Disable DMA to transfer data via AHB bus"]
174    DISABLE = 0,
175    #[doc = "1: Enable DMA to transfer data"]
176    ENABLE = 1,
177}
178impl From<DMA_ENB_A> for bool {
179    #[inline(always)]
180    fn from(variant: DMA_ENB_A) -> Self {
181        variant as u8 != 0
182    }
183}
184impl DMA_ENB_R {
185    #[doc = "Get enumerated values variant"]
186    #[inline(always)]
187    pub const fn variant(&self) -> DMA_ENB_A {
188        match self.bits {
189            false => DMA_ENB_A::DISABLE,
190            true => DMA_ENB_A::ENABLE,
191        }
192    }
193    #[doc = "Disable DMA to transfer data via AHB bus"]
194    #[inline(always)]
195    pub fn is_disable(&self) -> bool {
196        *self == DMA_ENB_A::DISABLE
197    }
198    #[doc = "Enable DMA to transfer data"]
199    #[inline(always)]
200    pub fn is_enable(&self) -> bool {
201        *self == DMA_ENB_A::ENABLE
202    }
203}
204#[doc = "Field `dma_enb` writer - DMA Global Enable"]
205pub type DMA_ENB_W<'a, REG> = crate::BitWriter<'a, REG, DMA_ENB_A>;
206impl<'a, REG> DMA_ENB_W<'a, REG>
207where
208    REG: crate::Writable + crate::RegisterSpec,
209{
210    #[doc = "Disable DMA to transfer data via AHB bus"]
211    #[inline(always)]
212    pub fn disable(self) -> &'a mut crate::W<REG> {
213        self.variant(DMA_ENB_A::DISABLE)
214    }
215    #[doc = "Enable DMA to transfer data"]
216    #[inline(always)]
217    pub fn enable(self) -> &'a mut crate::W<REG> {
218        self.variant(DMA_ENB_A::ENABLE)
219    }
220}
221#[doc = "Field `cd_dbc_enb` reader - Card Detect (Data\\[3\\] status) De-bounce Enable"]
222pub type CD_DBC_ENB_R = crate::BitReader<CD_DBC_ENB_A>;
223#[doc = "Card Detect (Data\\[3\\] status) De-bounce Enable\n\nValue on reset: 0"]
224#[derive(Clone, Copy, Debug, PartialEq, Eq)]
225pub enum CD_DBC_ENB_A {
226    #[doc = "0: Disable de-bounce"]
227    DISABLE = 0,
228    #[doc = "1: Enable de-bounce"]
229    ENABLE = 1,
230}
231impl From<CD_DBC_ENB_A> for bool {
232    #[inline(always)]
233    fn from(variant: CD_DBC_ENB_A) -> Self {
234        variant as u8 != 0
235    }
236}
237impl CD_DBC_ENB_R {
238    #[doc = "Get enumerated values variant"]
239    #[inline(always)]
240    pub const fn variant(&self) -> CD_DBC_ENB_A {
241        match self.bits {
242            false => CD_DBC_ENB_A::DISABLE,
243            true => CD_DBC_ENB_A::ENABLE,
244        }
245    }
246    #[doc = "Disable de-bounce"]
247    #[inline(always)]
248    pub fn is_disable(&self) -> bool {
249        *self == CD_DBC_ENB_A::DISABLE
250    }
251    #[doc = "Enable de-bounce"]
252    #[inline(always)]
253    pub fn is_enable(&self) -> bool {
254        *self == CD_DBC_ENB_A::ENABLE
255    }
256}
257#[doc = "Field `cd_dbc_enb` writer - Card Detect (Data\\[3\\] status) De-bounce Enable"]
258pub type CD_DBC_ENB_W<'a, REG> = crate::BitWriter<'a, REG, CD_DBC_ENB_A>;
259impl<'a, REG> CD_DBC_ENB_W<'a, REG>
260where
261    REG: crate::Writable + crate::RegisterSpec,
262{
263    #[doc = "Disable de-bounce"]
264    #[inline(always)]
265    pub fn disable(self) -> &'a mut crate::W<REG> {
266        self.variant(CD_DBC_ENB_A::DISABLE)
267    }
268    #[doc = "Enable de-bounce"]
269    #[inline(always)]
270    pub fn enable(self) -> &'a mut crate::W<REG> {
271        self.variant(CD_DBC_ENB_A::ENABLE)
272    }
273}
274#[doc = "Field `ddr_mod_sel` reader - DDR Mode Select"]
275pub type DDR_MOD_SEL_R = crate::BitReader<DDR_MOD_SEL_A>;
276#[doc = "DDR Mode Select\n\nValue on reset: 0"]
277#[derive(Clone, Copy, Debug, PartialEq, Eq)]
278pub enum DDR_MOD_SEL_A {
279    #[doc = "0: SDR mode"]
280    SDR = 0,
281    #[doc = "1: DDR mode"]
282    DDR = 1,
283}
284impl From<DDR_MOD_SEL_A> for bool {
285    #[inline(always)]
286    fn from(variant: DDR_MOD_SEL_A) -> Self {
287        variant as u8 != 0
288    }
289}
290impl DDR_MOD_SEL_R {
291    #[doc = "Get enumerated values variant"]
292    #[inline(always)]
293    pub const fn variant(&self) -> DDR_MOD_SEL_A {
294        match self.bits {
295            false => DDR_MOD_SEL_A::SDR,
296            true => DDR_MOD_SEL_A::DDR,
297        }
298    }
299    #[doc = "SDR mode"]
300    #[inline(always)]
301    pub fn is_sdr(&self) -> bool {
302        *self == DDR_MOD_SEL_A::SDR
303    }
304    #[doc = "DDR mode"]
305    #[inline(always)]
306    pub fn is_ddr(&self) -> bool {
307        *self == DDR_MOD_SEL_A::DDR
308    }
309}
310#[doc = "Field `ddr_mod_sel` writer - DDR Mode Select"]
311pub type DDR_MOD_SEL_W<'a, REG> = crate::BitWriter<'a, REG, DDR_MOD_SEL_A>;
312impl<'a, REG> DDR_MOD_SEL_W<'a, REG>
313where
314    REG: crate::Writable + crate::RegisterSpec,
315{
316    #[doc = "SDR mode"]
317    #[inline(always)]
318    pub fn sdr(self) -> &'a mut crate::W<REG> {
319        self.variant(DDR_MOD_SEL_A::SDR)
320    }
321    #[doc = "DDR mode"]
322    #[inline(always)]
323    pub fn ddr(self) -> &'a mut crate::W<REG> {
324        self.variant(DDR_MOD_SEL_A::DDR)
325    }
326}
327#[doc = "Field `time_unit_dat` reader - Time unit for data line"]
328pub type TIME_UNIT_DAT_R = crate::BitReader<TIME_UNIT_DAT_A>;
329#[doc = "Time unit for data line\n\nValue on reset: 0"]
330#[derive(Clone, Copy, Debug, PartialEq, Eq)]
331pub enum TIME_UNIT_DAT_A {
332    #[doc = "0: 1 card clock period"]
333    C1 = 0,
334    #[doc = "1: 256 card clock period"]
335    C256 = 1,
336}
337impl From<TIME_UNIT_DAT_A> for bool {
338    #[inline(always)]
339    fn from(variant: TIME_UNIT_DAT_A) -> Self {
340        variant as u8 != 0
341    }
342}
343impl TIME_UNIT_DAT_R {
344    #[doc = "Get enumerated values variant"]
345    #[inline(always)]
346    pub const fn variant(&self) -> TIME_UNIT_DAT_A {
347        match self.bits {
348            false => TIME_UNIT_DAT_A::C1,
349            true => TIME_UNIT_DAT_A::C256,
350        }
351    }
352    #[doc = "1 card clock period"]
353    #[inline(always)]
354    pub fn is_c1(&self) -> bool {
355        *self == TIME_UNIT_DAT_A::C1
356    }
357    #[doc = "256 card clock period"]
358    #[inline(always)]
359    pub fn is_c256(&self) -> bool {
360        *self == TIME_UNIT_DAT_A::C256
361    }
362}
363#[doc = "Field `time_unit_dat` writer - Time unit for data line"]
364pub type TIME_UNIT_DAT_W<'a, REG> = crate::BitWriter<'a, REG, TIME_UNIT_DAT_A>;
365impl<'a, REG> TIME_UNIT_DAT_W<'a, REG>
366where
367    REG: crate::Writable + crate::RegisterSpec,
368{
369    #[doc = "1 card clock period"]
370    #[inline(always)]
371    pub fn c1(self) -> &'a mut crate::W<REG> {
372        self.variant(TIME_UNIT_DAT_A::C1)
373    }
374    #[doc = "256 card clock period"]
375    #[inline(always)]
376    pub fn c256(self) -> &'a mut crate::W<REG> {
377        self.variant(TIME_UNIT_DAT_A::C256)
378    }
379}
380#[doc = "Field `time_unit_cmd` reader - Time unit for command line"]
381pub type TIME_UNIT_CMD_R = crate::BitReader<TIME_UNIT_CMD_A>;
382#[doc = "Time unit for command line\n\nValue on reset: 0"]
383#[derive(Clone, Copy, Debug, PartialEq, Eq)]
384pub enum TIME_UNIT_CMD_A {
385    #[doc = "0: 1 card clock period"]
386    C1 = 0,
387    #[doc = "1: 256 card clock period"]
388    C256 = 1,
389}
390impl From<TIME_UNIT_CMD_A> for bool {
391    #[inline(always)]
392    fn from(variant: TIME_UNIT_CMD_A) -> Self {
393        variant as u8 != 0
394    }
395}
396impl TIME_UNIT_CMD_R {
397    #[doc = "Get enumerated values variant"]
398    #[inline(always)]
399    pub const fn variant(&self) -> TIME_UNIT_CMD_A {
400        match self.bits {
401            false => TIME_UNIT_CMD_A::C1,
402            true => TIME_UNIT_CMD_A::C256,
403        }
404    }
405    #[doc = "1 card clock period"]
406    #[inline(always)]
407    pub fn is_c1(&self) -> bool {
408        *self == TIME_UNIT_CMD_A::C1
409    }
410    #[doc = "256 card clock period"]
411    #[inline(always)]
412    pub fn is_c256(&self) -> bool {
413        *self == TIME_UNIT_CMD_A::C256
414    }
415}
416#[doc = "Field `time_unit_cmd` writer - Time unit for command line"]
417pub type TIME_UNIT_CMD_W<'a, REG> = crate::BitWriter<'a, REG, TIME_UNIT_CMD_A>;
418impl<'a, REG> TIME_UNIT_CMD_W<'a, REG>
419where
420    REG: crate::Writable + crate::RegisterSpec,
421{
422    #[doc = "1 card clock period"]
423    #[inline(always)]
424    pub fn c1(self) -> &'a mut crate::W<REG> {
425        self.variant(TIME_UNIT_CMD_A::C1)
426    }
427    #[doc = "256 card clock period"]
428    #[inline(always)]
429    pub fn c256(self) -> &'a mut crate::W<REG> {
430        self.variant(TIME_UNIT_CMD_A::C256)
431    }
432}
433#[doc = "Field `fifo_ac_mod` reader - FIFO Accesss Mode"]
434pub type FIFO_AC_MOD_R = crate::BitReader<FIFO_AC_MOD_A>;
435#[doc = "FIFO Accesss Mode\n\nValue on reset: 0"]
436#[derive(Clone, Copy, Debug, PartialEq, Eq)]
437pub enum FIFO_AC_MOD_A {
438    #[doc = "0: DMA bus"]
439    DMA = 0,
440    #[doc = "1: AHB bus"]
441    AHB = 1,
442}
443impl From<FIFO_AC_MOD_A> for bool {
444    #[inline(always)]
445    fn from(variant: FIFO_AC_MOD_A) -> Self {
446        variant as u8 != 0
447    }
448}
449impl FIFO_AC_MOD_R {
450    #[doc = "Get enumerated values variant"]
451    #[inline(always)]
452    pub const fn variant(&self) -> FIFO_AC_MOD_A {
453        match self.bits {
454            false => FIFO_AC_MOD_A::DMA,
455            true => FIFO_AC_MOD_A::AHB,
456        }
457    }
458    #[doc = "DMA bus"]
459    #[inline(always)]
460    pub fn is_dma(&self) -> bool {
461        *self == FIFO_AC_MOD_A::DMA
462    }
463    #[doc = "AHB bus"]
464    #[inline(always)]
465    pub fn is_ahb(&self) -> bool {
466        *self == FIFO_AC_MOD_A::AHB
467    }
468}
469#[doc = "Field `fifo_ac_mod` writer - FIFO Accesss Mode"]
470pub type FIFO_AC_MOD_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_AC_MOD_A>;
471impl<'a, REG> FIFO_AC_MOD_W<'a, REG>
472where
473    REG: crate::Writable + crate::RegisterSpec,
474{
475    #[doc = "DMA bus"]
476    #[inline(always)]
477    pub fn dma(self) -> &'a mut crate::W<REG> {
478        self.variant(FIFO_AC_MOD_A::DMA)
479    }
480    #[doc = "AHB bus"]
481    #[inline(always)]
482    pub fn ahb(self) -> &'a mut crate::W<REG> {
483        self.variant(FIFO_AC_MOD_A::AHB)
484    }
485}
486impl R {
487    #[doc = "Bit 0 - Software Reset"]
488    #[inline(always)]
489    pub fn soft_rst(&self) -> SOFT_RST_R {
490        SOFT_RST_R::new((self.bits & 1) != 0)
491    }
492    #[doc = "Bit 1 - FIFO Reset"]
493    #[inline(always)]
494    pub fn fifo_rst(&self) -> FIFO_RST_R {
495        FIFO_RST_R::new(((self.bits >> 1) & 1) != 0)
496    }
497    #[doc = "Bit 2 - DMA Reset"]
498    #[inline(always)]
499    pub fn dma_rst(&self) -> DMA_RST_R {
500        DMA_RST_R::new(((self.bits >> 2) & 1) != 0)
501    }
502    #[doc = "Bit 4 - GLobal Interrupt Enable"]
503    #[inline(always)]
504    pub fn ine_enb(&self) -> INE_ENB_R {
505        INE_ENB_R::new(((self.bits >> 4) & 1) != 0)
506    }
507    #[doc = "Bit 5 - DMA Global Enable"]
508    #[inline(always)]
509    pub fn dma_enb(&self) -> DMA_ENB_R {
510        DMA_ENB_R::new(((self.bits >> 5) & 1) != 0)
511    }
512    #[doc = "Bit 8 - Card Detect (Data\\[3\\] status) De-bounce Enable"]
513    #[inline(always)]
514    pub fn cd_dbc_enb(&self) -> CD_DBC_ENB_R {
515        CD_DBC_ENB_R::new(((self.bits >> 8) & 1) != 0)
516    }
517    #[doc = "Bit 10 - DDR Mode Select"]
518    #[inline(always)]
519    pub fn ddr_mod_sel(&self) -> DDR_MOD_SEL_R {
520        DDR_MOD_SEL_R::new(((self.bits >> 10) & 1) != 0)
521    }
522    #[doc = "Bit 11 - Time unit for data line"]
523    #[inline(always)]
524    pub fn time_unit_dat(&self) -> TIME_UNIT_DAT_R {
525        TIME_UNIT_DAT_R::new(((self.bits >> 11) & 1) != 0)
526    }
527    #[doc = "Bit 12 - Time unit for command line"]
528    #[inline(always)]
529    pub fn time_unit_cmd(&self) -> TIME_UNIT_CMD_R {
530        TIME_UNIT_CMD_R::new(((self.bits >> 12) & 1) != 0)
531    }
532    #[doc = "Bit 31 - FIFO Accesss Mode"]
533    #[inline(always)]
534    pub fn fifo_ac_mod(&self) -> FIFO_AC_MOD_R {
535        FIFO_AC_MOD_R::new(((self.bits >> 31) & 1) != 0)
536    }
537}
538impl W {
539    #[doc = "Bit 0 - Software Reset"]
540    #[inline(always)]
541    #[must_use]
542    pub fn soft_rst(&mut self) -> SOFT_RST_W<SMHC_CTRL_SPEC> {
543        SOFT_RST_W::new(self, 0)
544    }
545    #[doc = "Bit 1 - FIFO Reset"]
546    #[inline(always)]
547    #[must_use]
548    pub fn fifo_rst(&mut self) -> FIFO_RST_W<SMHC_CTRL_SPEC> {
549        FIFO_RST_W::new(self, 1)
550    }
551    #[doc = "Bit 2 - DMA Reset"]
552    #[inline(always)]
553    #[must_use]
554    pub fn dma_rst(&mut self) -> DMA_RST_W<SMHC_CTRL_SPEC> {
555        DMA_RST_W::new(self, 2)
556    }
557    #[doc = "Bit 4 - GLobal Interrupt Enable"]
558    #[inline(always)]
559    #[must_use]
560    pub fn ine_enb(&mut self) -> INE_ENB_W<SMHC_CTRL_SPEC> {
561        INE_ENB_W::new(self, 4)
562    }
563    #[doc = "Bit 5 - DMA Global Enable"]
564    #[inline(always)]
565    #[must_use]
566    pub fn dma_enb(&mut self) -> DMA_ENB_W<SMHC_CTRL_SPEC> {
567        DMA_ENB_W::new(self, 5)
568    }
569    #[doc = "Bit 8 - Card Detect (Data\\[3\\] status) De-bounce Enable"]
570    #[inline(always)]
571    #[must_use]
572    pub fn cd_dbc_enb(&mut self) -> CD_DBC_ENB_W<SMHC_CTRL_SPEC> {
573        CD_DBC_ENB_W::new(self, 8)
574    }
575    #[doc = "Bit 10 - DDR Mode Select"]
576    #[inline(always)]
577    #[must_use]
578    pub fn ddr_mod_sel(&mut self) -> DDR_MOD_SEL_W<SMHC_CTRL_SPEC> {
579        DDR_MOD_SEL_W::new(self, 10)
580    }
581    #[doc = "Bit 11 - Time unit for data line"]
582    #[inline(always)]
583    #[must_use]
584    pub fn time_unit_dat(&mut self) -> TIME_UNIT_DAT_W<SMHC_CTRL_SPEC> {
585        TIME_UNIT_DAT_W::new(self, 11)
586    }
587    #[doc = "Bit 12 - Time unit for command line"]
588    #[inline(always)]
589    #[must_use]
590    pub fn time_unit_cmd(&mut self) -> TIME_UNIT_CMD_W<SMHC_CTRL_SPEC> {
591        TIME_UNIT_CMD_W::new(self, 12)
592    }
593    #[doc = "Bit 31 - FIFO Accesss Mode"]
594    #[inline(always)]
595    #[must_use]
596    pub fn fifo_ac_mod(&mut self) -> FIFO_AC_MOD_W<SMHC_CTRL_SPEC> {
597        FIFO_AC_MOD_W::new(self, 31)
598    }
599    #[doc = r" Writes raw bits to the register."]
600    #[doc = r""]
601    #[doc = r" # Safety"]
602    #[doc = r""]
603    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
604    #[inline(always)]
605    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
606        self.bits = bits;
607        self
608    }
609}
610#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
611pub struct SMHC_CTRL_SPEC;
612impl crate::RegisterSpec for SMHC_CTRL_SPEC {
613    type Ux = u32;
614}
615#[doc = "`read()` method returns [`smhc_ctrl::R`](R) reader structure"]
616impl crate::Readable for SMHC_CTRL_SPEC {}
617#[doc = "`write(|w| ..)` method takes [`smhc_ctrl::W`](W) writer structure"]
618impl crate::Writable for SMHC_CTRL_SPEC {
619    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
620    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
621}
622#[doc = "`reset()` method sets smhc_ctrl to value 0"]
623impl crate::Resettable for SMHC_CTRL_SPEC {
624    const RESET_VALUE: Self::Ux = 0;
625}
d1_pac/smhc/smhc_ctrl.rs

d1_pac/smhc/
smhc_ctrl.rs
