d1_pac/smhc/
smhc_clkdiv.rs

1#[doc = "Register `smhc_clkdiv` reader"]
2pub type R = crate::R<SMHC_CLKDIV_SPEC>;
3#[doc = "Register `smhc_clkdiv` writer"]
4pub type W = crate::W<SMHC_CLKDIV_SPEC>;
5#[doc = "Field `cclk_div` reader - Card Clock Divider"]
6pub type CCLK_DIV_R = crate::FieldReader;
7#[doc = "Field `cclk_div` writer - Card Clock Divider"]
8pub type CCLK_DIV_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `cclk_enb` reader - Card Clock Enable"]
10pub type CCLK_ENB_R = crate::BitReader<CCLK_ENB_A>;
11#[doc = "Card Clock Enable\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum CCLK_ENB_A {
14    #[doc = "0: Card Clock is off"]
15    OFF = 0,
16    #[doc = "1: Card Clock is on"]
17    ON = 1,
18}
19impl From<CCLK_ENB_A> for bool {
20    #[inline(always)]
21    fn from(variant: CCLK_ENB_A) -> Self {
22        variant as u8 != 0
23    }
24}
25impl CCLK_ENB_R {
26    #[doc = "Get enumerated values variant"]
27    #[inline(always)]
28    pub const fn variant(&self) -> CCLK_ENB_A {
29        match self.bits {
30            false => CCLK_ENB_A::OFF,
31            true => CCLK_ENB_A::ON,
32        }
33    }
34    #[doc = "Card Clock is off"]
35    #[inline(always)]
36    pub fn is_off(&self) -> bool {
37        *self == CCLK_ENB_A::OFF
38    }
39    #[doc = "Card Clock is on"]
40    #[inline(always)]
41    pub fn is_on(&self) -> bool {
42        *self == CCLK_ENB_A::ON
43    }
44}
45#[doc = "Field `cclk_enb` writer - Card Clock Enable"]
46pub type CCLK_ENB_W<'a, REG> = crate::BitWriter<'a, REG, CCLK_ENB_A>;
47impl<'a, REG> CCLK_ENB_W<'a, REG>
48where
49    REG: crate::Writable + crate::RegisterSpec,
50{
51    #[doc = "Card Clock is off"]
52    #[inline(always)]
53    pub fn off(self) -> &'a mut crate::W<REG> {
54        self.variant(CCLK_ENB_A::OFF)
55    }
56    #[doc = "Card Clock is on"]
57    #[inline(always)]
58    pub fn on(self) -> &'a mut crate::W<REG> {
59        self.variant(CCLK_ENB_A::ON)
60    }
61}
62#[doc = "Field `cclk_ctrl` reader - Card Clock Output Control"]
63pub type CCLK_CTRL_R = crate::BitReader<CCLK_CTRL_A>;
64#[doc = "Card Clock Output Control\n\nValue on reset: 0"]
65#[derive(Clone, Copy, Debug, PartialEq, Eq)]
66pub enum CCLK_CTRL_A {
67    #[doc = "0: Card clock is always on"]
68    ON = 0,
69    #[doc = "1: Turn off card clock when FSM is in IDLE state"]
70    OFF_IDLE = 1,
71}
72impl From<CCLK_CTRL_A> for bool {
73    #[inline(always)]
74    fn from(variant: CCLK_CTRL_A) -> Self {
75        variant as u8 != 0
76    }
77}
78impl CCLK_CTRL_R {
79    #[doc = "Get enumerated values variant"]
80    #[inline(always)]
81    pub const fn variant(&self) -> CCLK_CTRL_A {
82        match self.bits {
83            false => CCLK_CTRL_A::ON,
84            true => CCLK_CTRL_A::OFF_IDLE,
85        }
86    }
87    #[doc = "Card clock is always on"]
88    #[inline(always)]
89    pub fn is_on(&self) -> bool {
90        *self == CCLK_CTRL_A::ON
91    }
92    #[doc = "Turn off card clock when FSM is in IDLE state"]
93    #[inline(always)]
94    pub fn is_off_idle(&self) -> bool {
95        *self == CCLK_CTRL_A::OFF_IDLE
96    }
97}
98#[doc = "Field `cclk_ctrl` writer - Card Clock Output Control"]
99pub type CCLK_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, CCLK_CTRL_A>;
100impl<'a, REG> CCLK_CTRL_W<'a, REG>
101where
102    REG: crate::Writable + crate::RegisterSpec,
103{
104    #[doc = "Card clock is always on"]
105    #[inline(always)]
106    pub fn on(self) -> &'a mut crate::W<REG> {
107        self.variant(CCLK_CTRL_A::ON)
108    }
109    #[doc = "Turn off card clock when FSM is in IDLE state"]
110    #[inline(always)]
111    pub fn off_idle(self) -> &'a mut crate::W<REG> {
112        self.variant(CCLK_CTRL_A::OFF_IDLE)
113    }
114}
115#[doc = "Field `mask_data0` reader - "]
116pub type MASK_DATA0_R = crate::BitReader<MASK_DATA0_A>;
117#[doc = "\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119pub enum MASK_DATA0_A {
120    #[doc = "0: Do not mask data0 when update clock"]
121    NOT_MASK = 0,
122    #[doc = "1: Mask data0 when update clock"]
123    MASK = 1,
124}
125impl From<MASK_DATA0_A> for bool {
126    #[inline(always)]
127    fn from(variant: MASK_DATA0_A) -> Self {
128        variant as u8 != 0
129    }
130}
131impl MASK_DATA0_R {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub const fn variant(&self) -> MASK_DATA0_A {
135        match self.bits {
136            false => MASK_DATA0_A::NOT_MASK,
137            true => MASK_DATA0_A::MASK,
138        }
139    }
140    #[doc = "Do not mask data0 when update clock"]
141    #[inline(always)]
142    pub fn is_not_mask(&self) -> bool {
143        *self == MASK_DATA0_A::NOT_MASK
144    }
145    #[doc = "Mask data0 when update clock"]
146    #[inline(always)]
147    pub fn is_mask(&self) -> bool {
148        *self == MASK_DATA0_A::MASK
149    }
150}
151#[doc = "Field `mask_data0` writer - "]
152pub type MASK_DATA0_W<'a, REG> = crate::BitWriter<'a, REG, MASK_DATA0_A>;
153impl<'a, REG> MASK_DATA0_W<'a, REG>
154where
155    REG: crate::Writable + crate::RegisterSpec,
156{
157    #[doc = "Do not mask data0 when update clock"]
158    #[inline(always)]
159    pub fn not_mask(self) -> &'a mut crate::W<REG> {
160        self.variant(MASK_DATA0_A::NOT_MASK)
161    }
162    #[doc = "Mask data0 when update clock"]
163    #[inline(always)]
164    pub fn mask(self) -> &'a mut crate::W<REG> {
165        self.variant(MASK_DATA0_A::MASK)
166    }
167}
168impl R {
169    #[doc = "Bits 0:7 - Card Clock Divider"]
170    #[inline(always)]
171    pub fn cclk_div(&self) -> CCLK_DIV_R {
172        CCLK_DIV_R::new((self.bits & 0xff) as u8)
173    }
174    #[doc = "Bit 16 - Card Clock Enable"]
175    #[inline(always)]
176    pub fn cclk_enb(&self) -> CCLK_ENB_R {
177        CCLK_ENB_R::new(((self.bits >> 16) & 1) != 0)
178    }
179    #[doc = "Bit 17 - Card Clock Output Control"]
180    #[inline(always)]
181    pub fn cclk_ctrl(&self) -> CCLK_CTRL_R {
182        CCLK_CTRL_R::new(((self.bits >> 17) & 1) != 0)
183    }
184    #[doc = "Bit 31"]
185    #[inline(always)]
186    pub fn mask_data0(&self) -> MASK_DATA0_R {
187        MASK_DATA0_R::new(((self.bits >> 31) & 1) != 0)
188    }
189}
190impl W {
191    #[doc = "Bits 0:7 - Card Clock Divider"]
192    #[inline(always)]
193    #[must_use]
194    pub fn cclk_div(&mut self) -> CCLK_DIV_W<SMHC_CLKDIV_SPEC> {
195        CCLK_DIV_W::new(self, 0)
196    }
197    #[doc = "Bit 16 - Card Clock Enable"]
198    #[inline(always)]
199    #[must_use]
200    pub fn cclk_enb(&mut self) -> CCLK_ENB_W<SMHC_CLKDIV_SPEC> {
201        CCLK_ENB_W::new(self, 16)
202    }
203    #[doc = "Bit 17 - Card Clock Output Control"]
204    #[inline(always)]
205    #[must_use]
206    pub fn cclk_ctrl(&mut self) -> CCLK_CTRL_W<SMHC_CLKDIV_SPEC> {
207        CCLK_CTRL_W::new(self, 17)
208    }
209    #[doc = "Bit 31"]
210    #[inline(always)]
211    #[must_use]
212    pub fn mask_data0(&mut self) -> MASK_DATA0_W<SMHC_CLKDIV_SPEC> {
213        MASK_DATA0_W::new(self, 31)
214    }
215    #[doc = r" Writes raw bits to the register."]
216    #[doc = r""]
217    #[doc = r" # Safety"]
218    #[doc = r""]
219    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
220    #[inline(always)]
221    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
222        self.bits = bits;
223        self
224    }
225}
226#[doc = "Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_clkdiv::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_clkdiv::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
227pub struct SMHC_CLKDIV_SPEC;
228impl crate::RegisterSpec for SMHC_CLKDIV_SPEC {
229    type Ux = u32;
230}
231#[doc = "`read()` method returns [`smhc_clkdiv::R`](R) reader structure"]
232impl crate::Readable for SMHC_CLKDIV_SPEC {}
233#[doc = "`write(|w| ..)` method takes [`smhc_clkdiv::W`](W) writer structure"]
234impl crate::Writable for SMHC_CLKDIV_SPEC {
235    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
236    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
237}
238#[doc = "`reset()` method sets smhc_clkdiv to value 0"]
239impl crate::Resettable for SMHC_CLKDIV_SPEC {
240    const RESET_VALUE: Self::Ux = 0;
241}
d1_pac/smhc/smhc_clkdiv.rs

d1_pac/smhc/
smhc_clkdiv.rs
