d1_pac/smhc/
emmc_ddr_sbit_det.rs

1#[doc = "Register `emmc_ddr_sbit_det` reader"]
2pub type R = crate::R<EMMC_DDR_SBIT_DET_SPEC>;
3#[doc = "Register `emmc_ddr_sbit_det` writer"]
4pub type W = crate::W<EMMC_DDR_SBIT_DET_SPEC>;
5#[doc = "Field `half_start_bit` reader - Control for start bit detection mechanism inside mstorage based on duration of start bit"]
6pub type HALF_START_BIT_R = crate::BitReader<HALF_START_BIT_A>;
7#[doc = "Control for start bit detection mechanism inside mstorage based on duration of start bit\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum HALF_START_BIT_A {
10    #[doc = "0: Full cycle"]
11    FULL = 0,
12    #[doc = "1: Less than one full cycle"]
13    LESS = 1,
14}
15impl From<HALF_START_BIT_A> for bool {
16    #[inline(always)]
17    fn from(variant: HALF_START_BIT_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl HALF_START_BIT_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> HALF_START_BIT_A {
25        match self.bits {
26            false => HALF_START_BIT_A::FULL,
27            true => HALF_START_BIT_A::LESS,
28        }
29    }
30    #[doc = "Full cycle"]
31    #[inline(always)]
32    pub fn is_full(&self) -> bool {
33        *self == HALF_START_BIT_A::FULL
34    }
35    #[doc = "Less than one full cycle"]
36    #[inline(always)]
37    pub fn is_less(&self) -> bool {
38        *self == HALF_START_BIT_A::LESS
39    }
40}
41#[doc = "Field `half_start_bit` writer - Control for start bit detection mechanism inside mstorage based on duration of start bit"]
42pub type HALF_START_BIT_W<'a, REG> = crate::BitWriter<'a, REG, HALF_START_BIT_A>;
43impl<'a, REG> HALF_START_BIT_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Full cycle"]
48    #[inline(always)]
49    pub fn full(self) -> &'a mut crate::W<REG> {
50        self.variant(HALF_START_BIT_A::FULL)
51    }
52    #[doc = "Less than one full cycle"]
53    #[inline(always)]
54    pub fn less(self) -> &'a mut crate::W<REG> {
55        self.variant(HALF_START_BIT_A::LESS)
56    }
57}
58#[doc = "Field `hs400_md_en` reader - HS400 Mode Enable"]
59pub type HS400_MD_EN_R = crate::BitReader<HS400_MD_EN_A>;
60#[doc = "HS400 Mode Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum HS400_MD_EN_A {
63    #[doc = "0: Disabled"]
64    DISABLED = 0,
65    #[doc = "1: Enabled"]
66    ENABLED = 1,
67}
68impl From<HS400_MD_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: HS400_MD_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl HS400_MD_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> HS400_MD_EN_A {
78        match self.bits {
79            false => HS400_MD_EN_A::DISABLED,
80            true => HS400_MD_EN_A::ENABLED,
81        }
82    }
83    #[doc = "Disabled"]
84    #[inline(always)]
85    pub fn is_disabled(&self) -> bool {
86        *self == HS400_MD_EN_A::DISABLED
87    }
88    #[doc = "Enabled"]
89    #[inline(always)]
90    pub fn is_enabled(&self) -> bool {
91        *self == HS400_MD_EN_A::ENABLED
92    }
93}
94#[doc = "Field `hs400_md_en` writer - HS400 Mode Enable"]
95pub type HS400_MD_EN_W<'a, REG> = crate::BitWriter<'a, REG, HS400_MD_EN_A>;
96impl<'a, REG> HS400_MD_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disabled"]
101    #[inline(always)]
102    pub fn disabled(self) -> &'a mut crate::W<REG> {
103        self.variant(HS400_MD_EN_A::DISABLED)
104    }
105    #[doc = "Enabled"]
106    #[inline(always)]
107    pub fn enabled(self) -> &'a mut crate::W<REG> {
108        self.variant(HS400_MD_EN_A::ENABLED)
109    }
110}
111impl R {
112    #[doc = "Bit 0 - Control for start bit detection mechanism inside mstorage based on duration of start bit"]
113    #[inline(always)]
114    pub fn half_start_bit(&self) -> HALF_START_BIT_R {
115        HALF_START_BIT_R::new((self.bits & 1) != 0)
116    }
117    #[doc = "Bit 31 - HS400 Mode Enable"]
118    #[inline(always)]
119    pub fn hs400_md_en(&self) -> HS400_MD_EN_R {
120        HS400_MD_EN_R::new(((self.bits >> 31) & 1) != 0)
121    }
122}
123impl W {
124    #[doc = "Bit 0 - Control for start bit detection mechanism inside mstorage based on duration of start bit"]
125    #[inline(always)]
126    #[must_use]
127    pub fn half_start_bit(&mut self) -> HALF_START_BIT_W<EMMC_DDR_SBIT_DET_SPEC> {
128        HALF_START_BIT_W::new(self, 0)
129    }
130    #[doc = "Bit 31 - HS400 Mode Enable"]
131    #[inline(always)]
132    #[must_use]
133    pub fn hs400_md_en(&mut self) -> HS400_MD_EN_W<EMMC_DDR_SBIT_DET_SPEC> {
134        HS400_MD_EN_W::new(self, 31)
135    }
136    #[doc = r" Writes raw bits to the register."]
137    #[doc = r""]
138    #[doc = r" # Safety"]
139    #[doc = r""]
140    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
141    #[inline(always)]
142    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
143        self.bits = bits;
144        self
145    }
146}
147#[doc = "eMMC4.5 DDR Start Bit Detection Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emmc_ddr_sbit_det::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emmc_ddr_sbit_det::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
148pub struct EMMC_DDR_SBIT_DET_SPEC;
149impl crate::RegisterSpec for EMMC_DDR_SBIT_DET_SPEC {
150    type Ux = u32;
151}
152#[doc = "`read()` method returns [`emmc_ddr_sbit_det::R`](R) reader structure"]
153impl crate::Readable for EMMC_DDR_SBIT_DET_SPEC {}
154#[doc = "`write(|w| ..)` method takes [`emmc_ddr_sbit_det::W`](W) writer structure"]
155impl crate::Writable for EMMC_DDR_SBIT_DET_SPEC {
156    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
157    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
158}
159#[doc = "`reset()` method sets emmc_ddr_sbit_det to value 0"]
160impl crate::Resettable for EMMC_DDR_SBIT_DET_SPEC {
161    const RESET_VALUE: Self::Ux = 0;
162}
d1_pac/smhc/emmc_ddr_sbit_det.rs

d1_pac/smhc/
emmc_ddr_sbit_det.rs
