d1_pac/
smhc.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    smhc_ctrl: SMHC_CTRL,
5    smhc_clkdiv: SMHC_CLKDIV,
6    smhc_tmout: SMHC_TMOUT,
7    smhc_ctype: SMHC_CTYPE,
8    smhc_blksiz: SMHC_BLKSIZ,
9    smhc_bytcnt: SMHC_BYTCNT,
10    smhc_cmd: SMHC_CMD,
11    smhc_cmdarg: SMHC_CMDARG,
12    smhc_resp0: SMHC_RESP0,
13    smhc_resp1: SMHC_RESP1,
14    smhc_resp2: SMHC_RESP2,
15    smhc_resp3: SMHC_RESP3,
16    smhc_intmask: SMHC_INTMASK,
17    smhc_mintsts: SMHC_MINTSTS,
18    smhc_rintsts: SMHC_RINTSTS,
19    smhc_status: SMHC_STATUS,
20    smhc_fifoth: SMHC_FIFOTH,
21    smhc_funs: SMHC_FUNS,
22    smhc_tbc0: SMHC_TBC0,
23    smhc_tbc1: SMHC_TBC1,
24    smhc_dbgc: SMHC_DBGC,
25    smhc_csdc: SMHC_CSDC,
26    smhc_a12a: SMHC_A12A,
27    smhc_ntsr: SMHC_NTSR,
28    _reserved24: [u8; 0x18],
29    smhc_hwrst: SMHC_HWRST,
30    _reserved25: [u8; 0x04],
31    smhc_idmac: SMHC_IDMAC,
32    smhc_dlba: SMHC_DLBA,
33    smhc_idst: SMHC_IDST,
34    smhc_idie: SMHC_IDIE,
35    _reserved29: [u8; 0x70],
36    smhc_thld: SMHC_THLD,
37    smhc_sfc: SMHC_SFC,
38    smhc_a23a: SMHC_A23A,
39    emmc_ddr_sbit_det: EMMC_DDR_SBIT_DET,
40    _reserved33: [u8; 0x28],
41    smhc_ext_cmd: SMHC_EXT_CMD,
42    smhc_ext_resp: SMHC_EXT_RESP,
43    smhc_drv_dl: SMHC_DRV_DL,
44    smhc_smap_dl: SMHC_SMAP_DL,
45    smhc_ds_dl: SMHC_DS_DL,
46    smhc_hs400_dl: SMHC_HS400_DL,
47    _reserved39: [u8; 0xb0],
48    smhc_fifo: SMHC_FIFO,
49}
50impl RegisterBlock {
51    #[doc = "0x00 - Control Register"]
52    #[inline(always)]
53    pub const fn smhc_ctrl(&self) -> &SMHC_CTRL {
54        &self.smhc_ctrl
55    }
56    #[doc = "0x04 - Clock Control Register"]
57    #[inline(always)]
58    pub const fn smhc_clkdiv(&self) -> &SMHC_CLKDIV {
59        &self.smhc_clkdiv
60    }
61    #[doc = "0x08 - Time Out Register"]
62    #[inline(always)]
63    pub const fn smhc_tmout(&self) -> &SMHC_TMOUT {
64        &self.smhc_tmout
65    }
66    #[doc = "0x0c - Bus Width Register"]
67    #[inline(always)]
68    pub const fn smhc_ctype(&self) -> &SMHC_CTYPE {
69        &self.smhc_ctype
70    }
71    #[doc = "0x10 - Block Size Register"]
72    #[inline(always)]
73    pub const fn smhc_blksiz(&self) -> &SMHC_BLKSIZ {
74        &self.smhc_blksiz
75    }
76    #[doc = "0x14 - Byte Count Register"]
77    #[inline(always)]
78    pub const fn smhc_bytcnt(&self) -> &SMHC_BYTCNT {
79        &self.smhc_bytcnt
80    }
81    #[doc = "0x18 - Command Register"]
82    #[inline(always)]
83    pub const fn smhc_cmd(&self) -> &SMHC_CMD {
84        &self.smhc_cmd
85    }
86    #[doc = "0x1c - Command Argument Register"]
87    #[inline(always)]
88    pub const fn smhc_cmdarg(&self) -> &SMHC_CMDARG {
89        &self.smhc_cmdarg
90    }
91    #[doc = "0x20 - Response 0 Register"]
92    #[inline(always)]
93    pub const fn smhc_resp0(&self) -> &SMHC_RESP0 {
94        &self.smhc_resp0
95    }
96    #[doc = "0x24 - Response 1 Register"]
97    #[inline(always)]
98    pub const fn smhc_resp1(&self) -> &SMHC_RESP1 {
99        &self.smhc_resp1
100    }
101    #[doc = "0x28 - Response 2 Register"]
102    #[inline(always)]
103    pub const fn smhc_resp2(&self) -> &SMHC_RESP2 {
104        &self.smhc_resp2
105    }
106    #[doc = "0x2c - Response 3 Register"]
107    #[inline(always)]
108    pub const fn smhc_resp3(&self) -> &SMHC_RESP3 {
109        &self.smhc_resp3
110    }
111    #[doc = "0x30 - Interrupt Mask Register"]
112    #[inline(always)]
113    pub const fn smhc_intmask(&self) -> &SMHC_INTMASK {
114        &self.smhc_intmask
115    }
116    #[doc = "0x34 - Masked Interrupt Status Register"]
117    #[inline(always)]
118    pub const fn smhc_mintsts(&self) -> &SMHC_MINTSTS {
119        &self.smhc_mintsts
120    }
121    #[doc = "0x38 - Raw Interrupt Status Register"]
122    #[inline(always)]
123    pub const fn smhc_rintsts(&self) -> &SMHC_RINTSTS {
124        &self.smhc_rintsts
125    }
126    #[doc = "0x3c - Status Register"]
127    #[inline(always)]
128    pub const fn smhc_status(&self) -> &SMHC_STATUS {
129        &self.smhc_status
130    }
131    #[doc = "0x40 - FIFO Water Level Register"]
132    #[inline(always)]
133    pub const fn smhc_fifoth(&self) -> &SMHC_FIFOTH {
134        &self.smhc_fifoth
135    }
136    #[doc = "0x44 - FIFO Function Select Register"]
137    #[inline(always)]
138    pub const fn smhc_funs(&self) -> &SMHC_FUNS {
139        &self.smhc_funs
140    }
141    #[doc = "0x48 - Transferred Byte Count between Controller and Card"]
142    #[inline(always)]
143    pub const fn smhc_tbc0(&self) -> &SMHC_TBC0 {
144        &self.smhc_tbc0
145    }
146    #[doc = "0x4c - Transferred Byte Count between Host Memory and Internal FIFO"]
147    #[inline(always)]
148    pub const fn smhc_tbc1(&self) -> &SMHC_TBC1 {
149        &self.smhc_tbc1
150    }
151    #[doc = "0x50 - Current Debug Control Register"]
152    #[inline(always)]
153    pub const fn smhc_dbgc(&self) -> &SMHC_DBGC {
154        &self.smhc_dbgc
155    }
156    #[doc = "0x54 - CRC Status Detect Control Registers"]
157    #[inline(always)]
158    pub const fn smhc_csdc(&self) -> &SMHC_CSDC {
159        &self.smhc_csdc
160    }
161    #[doc = "0x58 - Auto Command 12 Argument Register"]
162    #[inline(always)]
163    pub const fn smhc_a12a(&self) -> &SMHC_A12A {
164        &self.smhc_a12a
165    }
166    #[doc = "0x5c - SD New Timing Set Register"]
167    #[inline(always)]
168    pub const fn smhc_ntsr(&self) -> &SMHC_NTSR {
169        &self.smhc_ntsr
170    }
171    #[doc = "0x78 - Hardware Reset Register"]
172    #[inline(always)]
173    pub const fn smhc_hwrst(&self) -> &SMHC_HWRST {
174        &self.smhc_hwrst
175    }
176    #[doc = "0x80 - IDMAC Control Register"]
177    #[inline(always)]
178    pub const fn smhc_idmac(&self) -> &SMHC_IDMAC {
179        &self.smhc_idmac
180    }
181    #[doc = "0x84 - Descriptor List Base Address Register"]
182    #[inline(always)]
183    pub const fn smhc_dlba(&self) -> &SMHC_DLBA {
184        &self.smhc_dlba
185    }
186    #[doc = "0x88 - IDMAC Status Register"]
187    #[inline(always)]
188    pub const fn smhc_idst(&self) -> &SMHC_IDST {
189        &self.smhc_idst
190    }
191    #[doc = "0x8c - IDMAC Interrupt Enable Register"]
192    #[inline(always)]
193    pub const fn smhc_idie(&self) -> &SMHC_IDIE {
194        &self.smhc_idie
195    }
196    #[doc = "0x100 - Card Threshold Control Register"]
197    #[inline(always)]
198    pub const fn smhc_thld(&self) -> &SMHC_THLD {
199        &self.smhc_thld
200    }
201    #[doc = "0x104 - Sample FIFO Control Register"]
202    #[inline(always)]
203    pub const fn smhc_sfc(&self) -> &SMHC_SFC {
204        &self.smhc_sfc
205    }
206    #[doc = "0x108 - Auto Command 23 Argument Register"]
207    #[inline(always)]
208    pub const fn smhc_a23a(&self) -> &SMHC_A23A {
209        &self.smhc_a23a
210    }
211    #[doc = "0x10c - eMMC4.5 DDR Start Bit Detection Control Register"]
212    #[inline(always)]
213    pub const fn emmc_ddr_sbit_det(&self) -> &EMMC_DDR_SBIT_DET {
214        &self.emmc_ddr_sbit_det
215    }
216    #[doc = "0x138 - Extended Command Register"]
217    #[inline(always)]
218    pub const fn smhc_ext_cmd(&self) -> &SMHC_EXT_CMD {
219        &self.smhc_ext_cmd
220    }
221    #[doc = "0x13c - Extended Response Register"]
222    #[inline(always)]
223    pub const fn smhc_ext_resp(&self) -> &SMHC_EXT_RESP {
224        &self.smhc_ext_resp
225    }
226    #[doc = "0x140 - Drive Delay Control Register"]
227    #[inline(always)]
228    pub const fn smhc_drv_dl(&self) -> &SMHC_DRV_DL {
229        &self.smhc_drv_dl
230    }
231    #[doc = "0x144 - Sample Delay Control Register"]
232    #[inline(always)]
233    pub const fn smhc_smap_dl(&self) -> &SMHC_SMAP_DL {
234        &self.smhc_smap_dl
235    }
236    #[doc = "0x148 - Data Strobe Delay Control Register"]
237    #[inline(always)]
238    pub const fn smhc_ds_dl(&self) -> &SMHC_DS_DL {
239        &self.smhc_ds_dl
240    }
241    #[doc = "0x14c - HS400 Delay Control Register"]
242    #[inline(always)]
243    pub const fn smhc_hs400_dl(&self) -> &SMHC_HS400_DL {
244        &self.smhc_hs400_dl
245    }
246    #[doc = "0x200 - Read/Write FIFO"]
247    #[inline(always)]
248    pub const fn smhc_fifo(&self) -> &SMHC_FIFO {
249        &self.smhc_fifo
250    }
251}
252#[doc = "smhc_ctrl (rw) register accessor: Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_ctrl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_ctrl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_ctrl`] module"]
253pub type SMHC_CTRL = crate::Reg<smhc_ctrl::SMHC_CTRL_SPEC>;
254#[doc = "Control Register"]
255pub mod smhc_ctrl;
256#[doc = "smhc_clkdiv (rw) register accessor: Clock Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_clkdiv::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_clkdiv::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_clkdiv`] module"]
257pub type SMHC_CLKDIV = crate::Reg<smhc_clkdiv::SMHC_CLKDIV_SPEC>;
258#[doc = "Clock Control Register"]
259pub mod smhc_clkdiv;
260#[doc = "smhc_tmout (rw) register accessor: Time Out Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_tmout::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_tmout::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_tmout`] module"]
261pub type SMHC_TMOUT = crate::Reg<smhc_tmout::SMHC_TMOUT_SPEC>;
262#[doc = "Time Out Register"]
263pub mod smhc_tmout;
264#[doc = "smhc_ctype (rw) register accessor: Bus Width Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_ctype::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_ctype::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_ctype`] module"]
265pub type SMHC_CTYPE = crate::Reg<smhc_ctype::SMHC_CTYPE_SPEC>;
266#[doc = "Bus Width Register"]
267pub mod smhc_ctype;
268#[doc = "smhc_blksiz (rw) register accessor: Block Size Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_blksiz::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_blksiz::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_blksiz`] module"]
269pub type SMHC_BLKSIZ = crate::Reg<smhc_blksiz::SMHC_BLKSIZ_SPEC>;
270#[doc = "Block Size Register"]
271pub mod smhc_blksiz;
272#[doc = "smhc_bytcnt (rw) register accessor: Byte Count Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_bytcnt::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_bytcnt::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_bytcnt`] module"]
273pub type SMHC_BYTCNT = crate::Reg<smhc_bytcnt::SMHC_BYTCNT_SPEC>;
274#[doc = "Byte Count Register"]
275pub mod smhc_bytcnt;
276#[doc = "smhc_cmd (rw) register accessor: Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_cmd`] module"]
277pub type SMHC_CMD = crate::Reg<smhc_cmd::SMHC_CMD_SPEC>;
278#[doc = "Command Register"]
279pub mod smhc_cmd;
280#[doc = "smhc_cmdarg (rw) register accessor: Command Argument Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_cmdarg::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_cmdarg::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_cmdarg`] module"]
281pub type SMHC_CMDARG = crate::Reg<smhc_cmdarg::SMHC_CMDARG_SPEC>;
282#[doc = "Command Argument Register"]
283pub mod smhc_cmdarg;
284#[doc = "smhc_resp0 (r) register accessor: Response 0 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_resp0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_resp0`] module"]
285pub type SMHC_RESP0 = crate::Reg<smhc_resp0::SMHC_RESP0_SPEC>;
286#[doc = "Response 0 Register"]
287pub mod smhc_resp0;
288#[doc = "smhc_resp1 (r) register accessor: Response 1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_resp1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_resp1`] module"]
289pub type SMHC_RESP1 = crate::Reg<smhc_resp1::SMHC_RESP1_SPEC>;
290#[doc = "Response 1 Register"]
291pub mod smhc_resp1;
292#[doc = "smhc_resp2 (r) register accessor: Response 2 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_resp2::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_resp2`] module"]
293pub type SMHC_RESP2 = crate::Reg<smhc_resp2::SMHC_RESP2_SPEC>;
294#[doc = "Response 2 Register"]
295pub mod smhc_resp2;
296#[doc = "smhc_resp3 (r) register accessor: Response 3 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_resp3::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_resp3`] module"]
297pub type SMHC_RESP3 = crate::Reg<smhc_resp3::SMHC_RESP3_SPEC>;
298#[doc = "Response 3 Register"]
299pub mod smhc_resp3;
300#[doc = "smhc_intmask (rw) register accessor: Interrupt Mask Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_intmask::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_intmask::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_intmask`] module"]
301pub type SMHC_INTMASK = crate::Reg<smhc_intmask::SMHC_INTMASK_SPEC>;
302#[doc = "Interrupt Mask Register"]
303pub mod smhc_intmask;
304#[doc = "smhc_mintsts (r) register accessor: Masked Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_mintsts::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_mintsts`] module"]
305pub type SMHC_MINTSTS = crate::Reg<smhc_mintsts::SMHC_MINTSTS_SPEC>;
306#[doc = "Masked Interrupt Status Register"]
307pub mod smhc_mintsts;
308#[doc = "smhc_rintsts (rw) register accessor: Raw Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_rintsts::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_rintsts::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_rintsts`] module"]
309pub type SMHC_RINTSTS = crate::Reg<smhc_rintsts::SMHC_RINTSTS_SPEC>;
310#[doc = "Raw Interrupt Status Register"]
311pub mod smhc_rintsts;
312#[doc = "smhc_status (r) register accessor: Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_status::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_status`] module"]
313pub type SMHC_STATUS = crate::Reg<smhc_status::SMHC_STATUS_SPEC>;
314#[doc = "Status Register"]
315pub mod smhc_status;
316#[doc = "smhc_fifoth (rw) register accessor: FIFO Water Level Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_fifoth::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_fifoth::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_fifoth`] module"]
317pub type SMHC_FIFOTH = crate::Reg<smhc_fifoth::SMHC_FIFOTH_SPEC>;
318#[doc = "FIFO Water Level Register"]
319pub mod smhc_fifoth;
320#[doc = "smhc_funs (rw) register accessor: FIFO Function Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_funs::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_funs::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_funs`] module"]
321pub type SMHC_FUNS = crate::Reg<smhc_funs::SMHC_FUNS_SPEC>;
322#[doc = "FIFO Function Select Register"]
323pub mod smhc_funs;
324#[doc = "smhc_tbc0 (r) register accessor: Transferred Byte Count between Controller and Card\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_tbc0::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_tbc0`] module"]
325pub type SMHC_TBC0 = crate::Reg<smhc_tbc0::SMHC_TBC0_SPEC>;
326#[doc = "Transferred Byte Count between Controller and Card"]
327pub mod smhc_tbc0;
328#[doc = "smhc_tbc1 (r) register accessor: Transferred Byte Count between Host Memory and Internal FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_tbc1::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_tbc1`] module"]
329pub type SMHC_TBC1 = crate::Reg<smhc_tbc1::SMHC_TBC1_SPEC>;
330#[doc = "Transferred Byte Count between Host Memory and Internal FIFO"]
331pub mod smhc_tbc1;
332#[doc = "smhc_dbgc (rw) register accessor: Current Debug Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_dbgc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_dbgc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_dbgc`] module"]
333pub type SMHC_DBGC = crate::Reg<smhc_dbgc::SMHC_DBGC_SPEC>;
334#[doc = "Current Debug Control Register"]
335pub mod smhc_dbgc;
336#[doc = "smhc_csdc (rw) register accessor: CRC Status Detect Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_csdc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_csdc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_csdc`] module"]
337pub type SMHC_CSDC = crate::Reg<smhc_csdc::SMHC_CSDC_SPEC>;
338#[doc = "CRC Status Detect Control Registers"]
339pub mod smhc_csdc;
340#[doc = "smhc_a12a (rw) register accessor: Auto Command 12 Argument Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_a12a::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_a12a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_a12a`] module"]
341pub type SMHC_A12A = crate::Reg<smhc_a12a::SMHC_A12A_SPEC>;
342#[doc = "Auto Command 12 Argument Register"]
343pub mod smhc_a12a;
344#[doc = "smhc_ntsr (rw) register accessor: SD New Timing Set Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_ntsr::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_ntsr::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_ntsr`] module"]
345pub type SMHC_NTSR = crate::Reg<smhc_ntsr::SMHC_NTSR_SPEC>;
346#[doc = "SD New Timing Set Register"]
347pub mod smhc_ntsr;
348#[doc = "smhc_hwrst (rw) register accessor: Hardware Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_hwrst::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_hwrst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_hwrst`] module"]
349pub type SMHC_HWRST = crate::Reg<smhc_hwrst::SMHC_HWRST_SPEC>;
350#[doc = "Hardware Reset Register"]
351pub mod smhc_hwrst;
352#[doc = "smhc_idmac (rw) register accessor: IDMAC Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_idmac::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_idmac::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_idmac`] module"]
353pub type SMHC_IDMAC = crate::Reg<smhc_idmac::SMHC_IDMAC_SPEC>;
354#[doc = "IDMAC Control Register"]
355pub mod smhc_idmac;
356#[doc = "smhc_dlba (rw) register accessor: Descriptor List Base Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_dlba::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_dlba::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_dlba`] module"]
357pub type SMHC_DLBA = crate::Reg<smhc_dlba::SMHC_DLBA_SPEC>;
358#[doc = "Descriptor List Base Address Register"]
359pub mod smhc_dlba;
360#[doc = "smhc_idst (rw) register accessor: IDMAC Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_idst::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_idst::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_idst`] module"]
361pub type SMHC_IDST = crate::Reg<smhc_idst::SMHC_IDST_SPEC>;
362#[doc = "IDMAC Status Register"]
363pub mod smhc_idst;
364#[doc = "smhc_idie (rw) register accessor: IDMAC Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_idie::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_idie::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_idie`] module"]
365pub type SMHC_IDIE = crate::Reg<smhc_idie::SMHC_IDIE_SPEC>;
366#[doc = "IDMAC Interrupt Enable Register"]
367pub mod smhc_idie;
368#[doc = "smhc_thld (rw) register accessor: Card Threshold Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_thld::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_thld::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_thld`] module"]
369pub type SMHC_THLD = crate::Reg<smhc_thld::SMHC_THLD_SPEC>;
370#[doc = "Card Threshold Control Register"]
371pub mod smhc_thld;
372#[doc = "smhc_sfc (rw) register accessor: Sample FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_sfc::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_sfc::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_sfc`] module"]
373pub type SMHC_SFC = crate::Reg<smhc_sfc::SMHC_SFC_SPEC>;
374#[doc = "Sample FIFO Control Register"]
375pub mod smhc_sfc;
376#[doc = "smhc_a23a (rw) register accessor: Auto Command 23 Argument Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_a23a::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_a23a::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_a23a`] module"]
377pub type SMHC_A23A = crate::Reg<smhc_a23a::SMHC_A23A_SPEC>;
378#[doc = "Auto Command 23 Argument Register"]
379pub mod smhc_a23a;
380#[doc = "emmc_ddr_sbit_det (rw) register accessor: eMMC4.5 DDR Start Bit Detection Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`emmc_ddr_sbit_det::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`emmc_ddr_sbit_det::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emmc_ddr_sbit_det`] module"]
381pub type EMMC_DDR_SBIT_DET = crate::Reg<emmc_ddr_sbit_det::EMMC_DDR_SBIT_DET_SPEC>;
382#[doc = "eMMC4.5 DDR Start Bit Detection Control Register"]
383pub mod emmc_ddr_sbit_det;
384#[doc = "smhc_ext_cmd (rw) register accessor: Extended Command Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_ext_cmd::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_ext_cmd::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_ext_cmd`] module"]
385pub type SMHC_EXT_CMD = crate::Reg<smhc_ext_cmd::SMHC_EXT_CMD_SPEC>;
386#[doc = "Extended Command Register"]
387pub mod smhc_ext_cmd;
388#[doc = "smhc_ext_resp (r) register accessor: Extended Response Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_ext_resp::R`].  See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_ext_resp`] module"]
389pub type SMHC_EXT_RESP = crate::Reg<smhc_ext_resp::SMHC_EXT_RESP_SPEC>;
390#[doc = "Extended Response Register"]
391pub mod smhc_ext_resp;
392#[doc = "smhc_drv_dl (rw) register accessor: Drive Delay Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_drv_dl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_drv_dl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_drv_dl`] module"]
393pub type SMHC_DRV_DL = crate::Reg<smhc_drv_dl::SMHC_DRV_DL_SPEC>;
394#[doc = "Drive Delay Control Register"]
395pub mod smhc_drv_dl;
396#[doc = "smhc_smap_dl (rw) register accessor: Sample Delay Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_smap_dl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_smap_dl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_smap_dl`] module"]
397pub type SMHC_SMAP_DL = crate::Reg<smhc_smap_dl::SMHC_SMAP_DL_SPEC>;
398#[doc = "Sample Delay Control Register"]
399pub mod smhc_smap_dl;
400#[doc = "smhc_ds_dl (rw) register accessor: Data Strobe Delay Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_ds_dl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_ds_dl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_ds_dl`] module"]
401pub type SMHC_DS_DL = crate::Reg<smhc_ds_dl::SMHC_DS_DL_SPEC>;
402#[doc = "Data Strobe Delay Control Register"]
403pub mod smhc_ds_dl;
404#[doc = "smhc_hs400_dl (rw) register accessor: HS400 Delay Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_hs400_dl::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_hs400_dl::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_hs400_dl`] module"]
405pub type SMHC_HS400_DL = crate::Reg<smhc_hs400_dl::SMHC_HS400_DL_SPEC>;
406#[doc = "HS400 Delay Control Register"]
407pub mod smhc_hs400_dl;
408#[doc = "smhc_fifo (rw) register accessor: Read/Write FIFO\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`smhc_fifo::R`].  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`smhc_fifo::W`]. You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@smhc_fifo`] module"]
409pub type SMHC_FIFO = crate::Reg<smhc_fifo::SMHC_FIFO_SPEC>;
410#[doc = "Read/Write FIFO"]
411pub mod smhc_fifo;
d1_pac/smhc.rs

d1_pac/
smhc.rs
