d1_pac/rtc/
vdd_off_gating_ctrl.rs

1#[doc = "Register `vdd_off_gating_ctrl` reader"]
2pub type R = crate::R<VDD_OFF_GATING_CTRL_SPEC>;
3#[doc = "Register `vdd_off_gating_ctrl` writer"]
4pub type W = crate::W<VDD_OFF_GATING_CTRL_SPEC>;
5#[doc = "Field `vccio_det_bypass_en` reader - "]
6pub type VCCIO_DET_BYPASS_EN_R = crate::BitReader<VCCIO_DET_BYPASS_EN_A>;
7#[doc = "\n\nValue on reset: 1"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum VCCIO_DET_BYPASS_EN_A {
10    #[doc = "0: not bypass"]
11    NOT_BYPASS = 0,
12    #[doc = "1: bypass"]
13    BYPASS = 1,
14}
15impl From<VCCIO_DET_BYPASS_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: VCCIO_DET_BYPASS_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl VCCIO_DET_BYPASS_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> VCCIO_DET_BYPASS_EN_A {
25        match self.bits {
26            false => VCCIO_DET_BYPASS_EN_A::NOT_BYPASS,
27            true => VCCIO_DET_BYPASS_EN_A::BYPASS,
28        }
29    }
30    #[doc = "not bypass"]
31    #[inline(always)]
32    pub fn is_not_bypass(&self) -> bool {
33        *self == VCCIO_DET_BYPASS_EN_A::NOT_BYPASS
34    }
35    #[doc = "bypass"]
36    #[inline(always)]
37    pub fn is_bypass(&self) -> bool {
38        *self == VCCIO_DET_BYPASS_EN_A::BYPASS
39    }
40}
41#[doc = "Field `vccio_det_bypass_en` writer - "]
42pub type VCCIO_DET_BYPASS_EN_W<'a, REG> = crate::BitWriter<'a, REG, VCCIO_DET_BYPASS_EN_A>;
43impl<'a, REG> VCCIO_DET_BYPASS_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "not bypass"]
48    #[inline(always)]
49    pub fn not_bypass(self) -> &'a mut crate::W<REG> {
50        self.variant(VCCIO_DET_BYPASS_EN_A::NOT_BYPASS)
51    }
52    #[doc = "bypass"]
53    #[inline(always)]
54    pub fn bypass(self) -> &'a mut crate::W<REG> {
55        self.variant(VCCIO_DET_BYPASS_EN_A::BYPASS)
56    }
57}
58#[doc = "Field `vccio_det_spare` reader - - Bit\\[7:5\\]: Reserved, default=0\n- Bit\\[4\\]: Bypass debounce circuit, defaule=0\n- Bit\\[3\\]: Enable control, defaule=0 \n - 0: Disable VCC-IO detection\n - 1: Force the detection output\n- Bit\\[2:0\\]: Gear adjustment\n - 000: Detection threshold is 2.5 V\n - 001: Detection threshold is 2.6 V\n - 010: Detection threshold is 2.7 V (default)\n - 011: Detection threshold is 2.8 V\n - 100: Detection threshold is 2.9 V\n - 101: Detection threshold is 3 V\n - 110: N/A\n - 111: N/A"]
59pub type VCCIO_DET_SPARE_R = crate::FieldReader;
60#[doc = "Field `vccio_det_spare` writer - - Bit\\[7:5\\]: Reserved, default=0\n- Bit\\[4\\]: Bypass debounce circuit, defaule=0\n- Bit\\[3\\]: Enable control, defaule=0 \n - 0: Disable VCC-IO detection\n - 1: Force the detection output\n- Bit\\[2:0\\]: Gear adjustment\n - 000: Detection threshold is 2.5 V\n - 001: Detection threshold is 2.6 V\n - 010: Detection threshold is 2.7 V (default)\n - 011: Detection threshold is 2.8 V\n - 100: Detection threshold is 2.9 V\n - 101: Detection threshold is 3 V\n - 110: N/A\n - 111: N/A"]
61pub type VCCIO_DET_SPARE_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
62#[doc = "Field `pwroff_gat_rtc_cfg` writer - Power off gating control signal\n\n(For Debug Use Only)\n\nWhen use vdd_sys to RTC isolation software control, write this bit to 1. It will only be cleared by resetb release."]
63pub type PWROFF_GAT_RTC_CFG_W<'a, REG> = crate::BitWriter<'a, REG>;
64#[doc = "Field `key_field` writer - Key Field\n\nThis field should be filled with 0x16AA, and then the bit 15 can be configured."]
65pub type KEY_FIELD_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
66impl R {
67    #[doc = "Bit 0"]
68    #[inline(always)]
69    pub fn vccio_det_bypass_en(&self) -> VCCIO_DET_BYPASS_EN_R {
70        VCCIO_DET_BYPASS_EN_R::new((self.bits & 1) != 0)
71    }
72    #[doc = "Bits 4:11 - - Bit\\[7:5\\]: Reserved, default=0\n- Bit\\[4\\]: Bypass debounce circuit, defaule=0\n- Bit\\[3\\]: Enable control, defaule=0 \n - 0: Disable VCC-IO detection\n - 1: Force the detection output\n- Bit\\[2:0\\]: Gear adjustment\n - 000: Detection threshold is 2.5 V\n - 001: Detection threshold is 2.6 V\n - 010: Detection threshold is 2.7 V (default)\n - 011: Detection threshold is 2.8 V\n - 100: Detection threshold is 2.9 V\n - 101: Detection threshold is 3 V\n - 110: N/A\n - 111: N/A"]
73    #[inline(always)]
74    pub fn vccio_det_spare(&self) -> VCCIO_DET_SPARE_R {
75        VCCIO_DET_SPARE_R::new(((self.bits >> 4) & 0xff) as u8)
76    }
77}
78impl W {
79    #[doc = "Bit 0"]
80    #[inline(always)]
81    #[must_use]
82    pub fn vccio_det_bypass_en(&mut self) -> VCCIO_DET_BYPASS_EN_W<VDD_OFF_GATING_CTRL_SPEC> {
83        VCCIO_DET_BYPASS_EN_W::new(self, 0)
84    }
85    #[doc = "Bits 4:11 - - Bit\\[7:5\\]: Reserved, default=0\n- Bit\\[4\\]: Bypass debounce circuit, defaule=0\n- Bit\\[3\\]: Enable control, defaule=0 \n - 0: Disable VCC-IO detection\n - 1: Force the detection output\n- Bit\\[2:0\\]: Gear adjustment\n - 000: Detection threshold is 2.5 V\n - 001: Detection threshold is 2.6 V\n - 010: Detection threshold is 2.7 V (default)\n - 011: Detection threshold is 2.8 V\n - 100: Detection threshold is 2.9 V\n - 101: Detection threshold is 3 V\n - 110: N/A\n - 111: N/A"]
86    #[inline(always)]
87    #[must_use]
88    pub fn vccio_det_spare(&mut self) -> VCCIO_DET_SPARE_W<VDD_OFF_GATING_CTRL_SPEC> {
89        VCCIO_DET_SPARE_W::new(self, 4)
90    }
91    #[doc = "Bit 15 - Power off gating control signal\n\n(For Debug Use Only)\n\nWhen use vdd_sys to RTC isolation software control, write this bit to 1. It will only be cleared by resetb release."]
92    #[inline(always)]
93    #[must_use]
94    pub fn pwroff_gat_rtc_cfg(&mut self) -> PWROFF_GAT_RTC_CFG_W<VDD_OFF_GATING_CTRL_SPEC> {
95        PWROFF_GAT_RTC_CFG_W::new(self, 15)
96    }
97    #[doc = "Bits 16:31 - Key Field\n\nThis field should be filled with 0x16AA, and then the bit 15 can be configured."]
98    #[inline(always)]
99    #[must_use]
100    pub fn key_field(&mut self) -> KEY_FIELD_W<VDD_OFF_GATING_CTRL_SPEC> {
101        KEY_FIELD_W::new(self, 16)
102    }
103    #[doc = r" Writes raw bits to the register."]
104    #[doc = r""]
105    #[doc = r" # Safety"]
106    #[doc = r""]
107    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
108    #[inline(always)]
109    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
110        self.bits = bits;
111        self
112    }
113}
114#[doc = "VDD Off Gating Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`vdd_off_gating_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`vdd_off_gating_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
115pub struct VDD_OFF_GATING_CTRL_SPEC;
116impl crate::RegisterSpec for VDD_OFF_GATING_CTRL_SPEC {
117    type Ux = u32;
118}
119#[doc = "`read()` method returns [`vdd_off_gating_ctrl::R`](R) reader structure"]
120impl crate::Readable for VDD_OFF_GATING_CTRL_SPEC {}
121#[doc = "`write(|w| ..)` method takes [`vdd_off_gating_ctrl::W`](W) writer structure"]
122impl crate::Writable for VDD_OFF_GATING_CTRL_SPEC {
123    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
124    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
125}
126#[doc = "`reset()` method sets vdd_off_gating_ctrl to value 0x21"]
127impl crate::Resettable for VDD_OFF_GATING_CTRL_SPEC {
128    const RESET_VALUE: Self::Ux = 0x21;
129}
d1_pac/rtc/vdd_off_gating_ctrl.rs

d1_pac/rtc/
vdd_off_gating_ctrl.rs
