d1_pac/rtc/
fout_32k_ctrl_gating.rs

1#[doc = "Register `fout_32k_ctrl_gating` reader"]
2pub type R = crate::R<FOUT_32K_CTRL_GATING_SPEC>;
3#[doc = "Register `fout_32k_ctrl_gating` writer"]
4pub type W = crate::W<FOUT_32K_CTRL_GATING_SPEC>;
5#[doc = "Field `fanout_32k_gating` reader - LOSC out gating enable\n\nConfiguration of LOSC output, and there is no LOSC output by default."]
6pub type FANOUT_32K_GATING_R = crate::BitReader<FANOUT_32K_GATING_A>;
7#[doc = "LOSC out gating enable\n\nConfiguration of LOSC output, and there is no LOSC output by default.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum FANOUT_32K_GATING_A {
10    #[doc = "0: Mask LOSC output gating"]
11    MASK = 0,
12    #[doc = "1: Enable LOSC output gating"]
13    ENABLE = 1,
14}
15impl From<FANOUT_32K_GATING_A> for bool {
16    #[inline(always)]
17    fn from(variant: FANOUT_32K_GATING_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl FANOUT_32K_GATING_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> FANOUT_32K_GATING_A {
25        match self.bits {
26            false => FANOUT_32K_GATING_A::MASK,
27            true => FANOUT_32K_GATING_A::ENABLE,
28        }
29    }
30    #[doc = "Mask LOSC output gating"]
31    #[inline(always)]
32    pub fn is_mask(&self) -> bool {
33        *self == FANOUT_32K_GATING_A::MASK
34    }
35    #[doc = "Enable LOSC output gating"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == FANOUT_32K_GATING_A::ENABLE
39    }
40}
41#[doc = "Field `fanout_32k_gating` writer - LOSC out gating enable\n\nConfiguration of LOSC output, and there is no LOSC output by default."]
42pub type FANOUT_32K_GATING_W<'a, REG> = crate::BitWriter<'a, REG, FANOUT_32K_GATING_A>;
43impl<'a, REG> FANOUT_32K_GATING_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Mask LOSC output gating"]
48    #[inline(always)]
49    pub fn mask(self) -> &'a mut crate::W<REG> {
50        self.variant(FANOUT_32K_GATING_A::MASK)
51    }
52    #[doc = "Enable LOSC output gating"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(FANOUT_32K_GATING_A::ENABLE)
56    }
57}
58#[doc = "Field `losc_out_src_sel` reader - LOSC output source select"]
59pub type LOSC_OUT_SRC_SEL_R = crate::FieldReader<LOSC_OUT_SRC_SEL_A>;
60#[doc = "LOSC output source select\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62#[repr(u8)]
63pub enum LOSC_OUT_SRC_SEL_A {
64    #[doc = "0: RTC_32K (select by RC_CLK_SRC_SEL LOSC_SRC_SEL)"]
65    RTC_32K = 0,
66    #[doc = "1: LOSC"]
67    LOSC = 1,
68    #[doc = "2: HOSC divided 32K"]
69    HOSC = 2,
70}
71impl From<LOSC_OUT_SRC_SEL_A> for u8 {
72    #[inline(always)]
73    fn from(variant: LOSC_OUT_SRC_SEL_A) -> Self {
74        variant as _
75    }
76}
77impl crate::FieldSpec for LOSC_OUT_SRC_SEL_A {
78    type Ux = u8;
79}
80impl LOSC_OUT_SRC_SEL_R {
81    #[doc = "Get enumerated values variant"]
82    #[inline(always)]
83    pub const fn variant(&self) -> Option<LOSC_OUT_SRC_SEL_A> {
84        match self.bits {
85            0 => Some(LOSC_OUT_SRC_SEL_A::RTC_32K),
86            1 => Some(LOSC_OUT_SRC_SEL_A::LOSC),
87            2 => Some(LOSC_OUT_SRC_SEL_A::HOSC),
88            _ => None,
89        }
90    }
91    #[doc = "RTC_32K (select by RC_CLK_SRC_SEL LOSC_SRC_SEL)"]
92    #[inline(always)]
93    pub fn is_rtc_32k(&self) -> bool {
94        *self == LOSC_OUT_SRC_SEL_A::RTC_32K
95    }
96    #[doc = "LOSC"]
97    #[inline(always)]
98    pub fn is_losc(&self) -> bool {
99        *self == LOSC_OUT_SRC_SEL_A::LOSC
100    }
101    #[doc = "HOSC divided 32K"]
102    #[inline(always)]
103    pub fn is_hosc(&self) -> bool {
104        *self == LOSC_OUT_SRC_SEL_A::HOSC
105    }
106}
107#[doc = "Field `losc_out_src_sel` writer - LOSC output source select"]
108pub type LOSC_OUT_SRC_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, LOSC_OUT_SRC_SEL_A>;
109impl<'a, REG> LOSC_OUT_SRC_SEL_W<'a, REG>
110where
111    REG: crate::Writable + crate::RegisterSpec,
112    REG::Ux: From<u8>,
113{
114    #[doc = "RTC_32K (select by RC_CLK_SRC_SEL LOSC_SRC_SEL)"]
115    #[inline(always)]
116    pub fn rtc_32k(self) -> &'a mut crate::W<REG> {
117        self.variant(LOSC_OUT_SRC_SEL_A::RTC_32K)
118    }
119    #[doc = "LOSC"]
120    #[inline(always)]
121    pub fn losc(self) -> &'a mut crate::W<REG> {
122        self.variant(LOSC_OUT_SRC_SEL_A::LOSC)
123    }
124    #[doc = "HOSC divided 32K"]
125    #[inline(always)]
126    pub fn hosc(self) -> &'a mut crate::W<REG> {
127        self.variant(LOSC_OUT_SRC_SEL_A::HOSC)
128    }
129}
130#[doc = "Field `hosc_to_32k_divider_enable` reader - HOSC to 32k divider enable"]
131pub type HOSC_TO_32K_DIVIDER_ENABLE_R = crate::BitReader<HOSC_TO_32K_DIVIDER_ENABLE_A>;
132#[doc = "HOSC to 32k divider enable\n\nValue on reset: 0"]
133#[derive(Clone, Copy, Debug, PartialEq, Eq)]
134pub enum HOSC_TO_32K_DIVIDER_ENABLE_A {
135    #[doc = "0: Disable the hosc 24M to 32K divider circuit"]
136    DISABLE = 0,
137    #[doc = "1: Enable the hosc 24M to 32K divider circuit"]
138    ENABLE = 1,
139}
140impl From<HOSC_TO_32K_DIVIDER_ENABLE_A> for bool {
141    #[inline(always)]
142    fn from(variant: HOSC_TO_32K_DIVIDER_ENABLE_A) -> Self {
143        variant as u8 != 0
144    }
145}
146impl HOSC_TO_32K_DIVIDER_ENABLE_R {
147    #[doc = "Get enumerated values variant"]
148    #[inline(always)]
149    pub const fn variant(&self) -> HOSC_TO_32K_DIVIDER_ENABLE_A {
150        match self.bits {
151            false => HOSC_TO_32K_DIVIDER_ENABLE_A::DISABLE,
152            true => HOSC_TO_32K_DIVIDER_ENABLE_A::ENABLE,
153        }
154    }
155    #[doc = "Disable the hosc 24M to 32K divider circuit"]
156    #[inline(always)]
157    pub fn is_disable(&self) -> bool {
158        *self == HOSC_TO_32K_DIVIDER_ENABLE_A::DISABLE
159    }
160    #[doc = "Enable the hosc 24M to 32K divider circuit"]
161    #[inline(always)]
162    pub fn is_enable(&self) -> bool {
163        *self == HOSC_TO_32K_DIVIDER_ENABLE_A::ENABLE
164    }
165}
166#[doc = "Field `hosc_to_32k_divider_enable` writer - HOSC to 32k divider enable"]
167pub type HOSC_TO_32K_DIVIDER_ENABLE_W<'a, REG> =
168    crate::BitWriter<'a, REG, HOSC_TO_32K_DIVIDER_ENABLE_A>;
169impl<'a, REG> HOSC_TO_32K_DIVIDER_ENABLE_W<'a, REG>
170where
171    REG: crate::Writable + crate::RegisterSpec,
172{
173    #[doc = "Disable the hosc 24M to 32K divider circuit"]
174    #[inline(always)]
175    pub fn disable(self) -> &'a mut crate::W<REG> {
176        self.variant(HOSC_TO_32K_DIVIDER_ENABLE_A::DISABLE)
177    }
178    #[doc = "Enable the hosc 24M to 32K divider circuit"]
179    #[inline(always)]
180    pub fn enable(self) -> &'a mut crate::W<REG> {
181        self.variant(HOSC_TO_32K_DIVIDER_ENABLE_A::ENABLE)
182    }
183}
184impl R {
185    #[doc = "Bit 0 - LOSC out gating enable\n\nConfiguration of LOSC output, and there is no LOSC output by default."]
186    #[inline(always)]
187    pub fn fanout_32k_gating(&self) -> FANOUT_32K_GATING_R {
188        FANOUT_32K_GATING_R::new((self.bits & 1) != 0)
189    }
190    #[doc = "Bits 1:2 - LOSC output source select"]
191    #[inline(always)]
192    pub fn losc_out_src_sel(&self) -> LOSC_OUT_SRC_SEL_R {
193        LOSC_OUT_SRC_SEL_R::new(((self.bits >> 1) & 3) as u8)
194    }
195    #[doc = "Bit 16 - HOSC to 32k divider enable"]
196    #[inline(always)]
197    pub fn hosc_to_32k_divider_enable(&self) -> HOSC_TO_32K_DIVIDER_ENABLE_R {
198        HOSC_TO_32K_DIVIDER_ENABLE_R::new(((self.bits >> 16) & 1) != 0)
199    }
200}
201impl W {
202    #[doc = "Bit 0 - LOSC out gating enable\n\nConfiguration of LOSC output, and there is no LOSC output by default."]
203    #[inline(always)]
204    #[must_use]
205    pub fn fanout_32k_gating(&mut self) -> FANOUT_32K_GATING_W<FOUT_32K_CTRL_GATING_SPEC> {
206        FANOUT_32K_GATING_W::new(self, 0)
207    }
208    #[doc = "Bits 1:2 - LOSC output source select"]
209    #[inline(always)]
210    #[must_use]
211    pub fn losc_out_src_sel(&mut self) -> LOSC_OUT_SRC_SEL_W<FOUT_32K_CTRL_GATING_SPEC> {
212        LOSC_OUT_SRC_SEL_W::new(self, 1)
213    }
214    #[doc = "Bit 16 - HOSC to 32k divider enable"]
215    #[inline(always)]
216    #[must_use]
217    pub fn hosc_to_32k_divider_enable(
218        &mut self,
219    ) -> HOSC_TO_32K_DIVIDER_ENABLE_W<FOUT_32K_CTRL_GATING_SPEC> {
220        HOSC_TO_32K_DIVIDER_ENABLE_W::new(self, 16)
221    }
222    #[doc = r" Writes raw bits to the register."]
223    #[doc = r""]
224    #[doc = r" # Safety"]
225    #[doc = r""]
226    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
227    #[inline(always)]
228    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
229        self.bits = bits;
230        self
231    }
232}
233#[doc = "32K Fanout Control Gating Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fout_32k_ctrl_gating::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fout_32k_ctrl_gating::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
234pub struct FOUT_32K_CTRL_GATING_SPEC;
235impl crate::RegisterSpec for FOUT_32K_CTRL_GATING_SPEC {
236    type Ux = u32;
237}
238#[doc = "`read()` method returns [`fout_32k_ctrl_gating::R`](R) reader structure"]
239impl crate::Readable for FOUT_32K_CTRL_GATING_SPEC {}
240#[doc = "`write(|w| ..)` method takes [`fout_32k_ctrl_gating::W`](W) writer structure"]
241impl crate::Writable for FOUT_32K_CTRL_GATING_SPEC {
242    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
243    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
244}
245#[doc = "`reset()` method sets fout_32k_ctrl_gating to value 0"]
246impl crate::Resettable for FOUT_32K_CTRL_GATING_SPEC {
247    const RESET_VALUE: Self::Ux = 0;
248}
d1_pac/rtc/fout_32k_ctrl_gating.rs

d1_pac/rtc/
fout_32k_ctrl_gating.rs
