d1_pac/rtc/
dcxo_ctrl.rs

1#[doc = "Register `dcxo_ctrl` reader"]
2pub type R = crate::R<DCXO_CTRL_SPEC>;
3#[doc = "Register `dcxo_ctrl` writer"]
4pub type W = crate::W<DCXO_CTRL_SPEC>;
5#[doc = "Field `clk16m_rc_en` reader - The related register configuration is necessary to ensure the reset debounce circuit has a stable clock source. The first time SoC starts up, by default, the reset debounce circuit of SoC uses 32K divided by RC16M. In power-off, software reads the related bit to ensure whether EXT32K is working normally, if it is normal, first switch the clock source of debounce circuit to EXT32K, then close RC16M. Without EXT32K scenario or external RTC scenario, software confirms firstly whether EXT32K is working normally before switching, or software does not close RC16M."]
6pub type CLK16M_RC_EN_R = crate::BitReader<CLK16M_RC_EN_A>;
7#[doc = "The related register configuration is necessary to ensure the reset debounce circuit has a stable clock source. The first time SoC starts up, by default, the reset debounce circuit of SoC uses 32K divided by RC16M. In power-off, software reads the related bit to ensure whether EXT32K is working normally, if it is normal, first switch the clock source of debounce circuit to EXT32K, then close RC16M. Without EXT32K scenario or external RTC scenario, software confirms firstly whether EXT32K is working normally before switching, or software does not close RC16M.\n\nValue on reset: 1"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CLK16M_RC_EN_A {
10    #[doc = "1: Enable"]
11    ENABLE = 1,
12    #[doc = "0: Disable"]
13    DISABLE = 0,
14}
15impl From<CLK16M_RC_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: CLK16M_RC_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CLK16M_RC_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CLK16M_RC_EN_A {
25        match self.bits {
26            true => CLK16M_RC_EN_A::ENABLE,
27            false => CLK16M_RC_EN_A::DISABLE,
28        }
29    }
30    #[doc = "Enable"]
31    #[inline(always)]
32    pub fn is_enable(&self) -> bool {
33        *self == CLK16M_RC_EN_A::ENABLE
34    }
35    #[doc = "Disable"]
36    #[inline(always)]
37    pub fn is_disable(&self) -> bool {
38        *self == CLK16M_RC_EN_A::DISABLE
39    }
40}
41#[doc = "Field `clk16m_rc_en` writer - The related register configuration is necessary to ensure the reset debounce circuit has a stable clock source. The first time SoC starts up, by default, the reset debounce circuit of SoC uses 32K divided by RC16M. In power-off, software reads the related bit to ensure whether EXT32K is working normally, if it is normal, first switch the clock source of debounce circuit to EXT32K, then close RC16M. Without EXT32K scenario or external RTC scenario, software confirms firstly whether EXT32K is working normally before switching, or software does not close RC16M."]
42pub type CLK16M_RC_EN_W<'a, REG> = crate::BitWriter<'a, REG, CLK16M_RC_EN_A>;
43impl<'a, REG> CLK16M_RC_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Enable"]
48    #[inline(always)]
49    pub fn enable(self) -> &'a mut crate::W<REG> {
50        self.variant(CLK16M_RC_EN_A::ENABLE)
51    }
52    #[doc = "Disable"]
53    #[inline(always)]
54    pub fn disable(self) -> &'a mut crate::W<REG> {
55        self.variant(CLK16M_RC_EN_A::DISABLE)
56    }
57}
58#[doc = "Field `dcxo_en` reader - DCXO enable"]
59pub type DCXO_EN_R = crate::BitReader<DCXO_EN_A>;
60#[doc = "DCXO enable\n\nValue on reset: 1"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum DCXO_EN_A {
63    #[doc = "1: Enable"]
64    ENABLE = 1,
65    #[doc = "0: Disable"]
66    DISABLE = 0,
67}
68impl From<DCXO_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: DCXO_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl DCXO_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> DCXO_EN_A {
78        match self.bits {
79            true => DCXO_EN_A::ENABLE,
80            false => DCXO_EN_A::DISABLE,
81        }
82    }
83    #[doc = "Enable"]
84    #[inline(always)]
85    pub fn is_enable(&self) -> bool {
86        *self == DCXO_EN_A::ENABLE
87    }
88    #[doc = "Disable"]
89    #[inline(always)]
90    pub fn is_disable(&self) -> bool {
91        *self == DCXO_EN_A::DISABLE
92    }
93}
94#[doc = "Field `dcxo_en` writer - DCXO enable"]
95pub type DCXO_EN_W<'a, REG> = crate::BitWriter<'a, REG, DCXO_EN_A>;
96impl<'a, REG> DCXO_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Enable"]
101    #[inline(always)]
102    pub fn enable(self) -> &'a mut crate::W<REG> {
103        self.variant(DCXO_EN_A::ENABLE)
104    }
105    #[doc = "Disable"]
106    #[inline(always)]
107    pub fn disable(self) -> &'a mut crate::W<REG> {
108        self.variant(DCXO_EN_A::DISABLE)
109    }
110}
111#[doc = "Field `rsto_dly_sel` reader - For Debug Use Only.\n\nIt cannot configure to 0 in normal state."]
112pub type RSTO_DLY_SEL_R = crate::BitReader;
113#[doc = "Field `rsto_dly_sel` writer - For Debug Use Only.\n\nIt cannot configure to 0 in normal state."]
114pub type RSTO_DLY_SEL_W<'a, REG> = crate::BitWriter<'a, REG>;
115#[doc = "Field `dcxo_rfclk_enhance` reader - DCXO rfclk enhance\n\nEnhance driving capacity of output OUT_RF_REFCLK, 0x0 for 5 pF, 0x1 for 10 pF, 0x2 for 15 pF, 0x3 for 20 pF."]
116pub type DCXO_RFCLK_ENHANCE_R = crate::FieldReader;
117#[doc = "Field `dcxo_rfclk_enhance` writer - DCXO rfclk enhance\n\nEnhance driving capacity of output OUT_RF_REFCLK, 0x0 for 5 pF, 0x1 for 10 pF, 0x2 for 15 pF, 0x3 for 20 pF."]
118pub type DCXO_RFCLK_ENHANCE_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
119#[doc = "Field `xtal_mode` reader - Xtal mode enable signal, active high"]
120pub type XTAL_MODE_R = crate::BitReader<XTAL_MODE_A>;
121#[doc = "Xtal mode enable signal, active high\n\nValue on reset: 1"]
122#[derive(Clone, Copy, Debug, PartialEq, Eq)]
123pub enum XTAL_MODE_A {
124    #[doc = "0: For external clk input mode"]
125    FOR_EXTERNAL = 0,
126    #[doc = "1: For normal mode"]
127    FOR_NORMAL_MODE = 1,
128}
129impl From<XTAL_MODE_A> for bool {
130    #[inline(always)]
131    fn from(variant: XTAL_MODE_A) -> Self {
132        variant as u8 != 0
133    }
134}
135impl XTAL_MODE_R {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub const fn variant(&self) -> XTAL_MODE_A {
139        match self.bits {
140            false => XTAL_MODE_A::FOR_EXTERNAL,
141            true => XTAL_MODE_A::FOR_NORMAL_MODE,
142        }
143    }
144    #[doc = "For external clk input mode"]
145    #[inline(always)]
146    pub fn is_for_external(&self) -> bool {
147        *self == XTAL_MODE_A::FOR_EXTERNAL
148    }
149    #[doc = "For normal mode"]
150    #[inline(always)]
151    pub fn is_for_normal_mode(&self) -> bool {
152        *self == XTAL_MODE_A::FOR_NORMAL_MODE
153    }
154}
155#[doc = "Field `xtal_mode` writer - Xtal mode enable signal, active high"]
156pub type XTAL_MODE_W<'a, REG> = crate::BitWriter<'a, REG, XTAL_MODE_A>;
157impl<'a, REG> XTAL_MODE_W<'a, REG>
158where
159    REG: crate::Writable + crate::RegisterSpec,
160{
161    #[doc = "For external clk input mode"]
162    #[inline(always)]
163    pub fn for_external(self) -> &'a mut crate::W<REG> {
164        self.variant(XTAL_MODE_A::FOR_EXTERNAL)
165    }
166    #[doc = "For normal mode"]
167    #[inline(always)]
168    pub fn for_normal_mode(self) -> &'a mut crate::W<REG> {
169        self.variant(XTAL_MODE_A::FOR_NORMAL_MODE)
170    }
171}
172#[doc = "Field `dcxo_ldo_inrushb` reader - DCXO LDO driving capacity signal, active high"]
173pub type DCXO_LDO_INRUSHB_R = crate::BitReader;
174#[doc = "Field `dcxo_ldo_inrushb` writer - DCXO LDO driving capacity signal, active high"]
175pub type DCXO_LDO_INRUSHB_W<'a, REG> = crate::BitWriter<'a, REG>;
176#[doc = "Field `dcxo_bg` reader - DCXO bandgap output voltage"]
177pub type DCXO_BG_R = crate::FieldReader;
178#[doc = "Field `dcxo_bg` writer - DCXO bandgap output voltage"]
179pub type DCXO_BG_W<'a, REG> = crate::FieldWriter<'a, REG, 5>;
180#[doc = "Field `dcxo_trim` reader - DCXO cap array value\n\nThe capacity cell is 55 fF."]
181pub type DCXO_TRIM_R = crate::FieldReader;
182#[doc = "Field `dcxo_trim` writer - DCXO cap array value\n\nThe capacity cell is 55 fF."]
183pub type DCXO_TRIM_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
184#[doc = "Field `dcxo_ictrl` reader - DCXO current control value"]
185pub type DCXO_ICTRL_R = crate::FieldReader;
186#[doc = "Field `dcxo_ictrl` writer - DCXO current control value"]
187pub type DCXO_ICTRL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
188#[doc = "Field `clk_req_enb` reader - Clock REQ enable"]
189pub type CLK_REQ_ENB_R = crate::BitReader<CLK_REQ_ENB_A>;
190#[doc = "Clock REQ enable\n\nValue on reset: 1"]
191#[derive(Clone, Copy, Debug, PartialEq, Eq)]
192pub enum CLK_REQ_ENB_A {
193    #[doc = "0: Enable DCXO wake up function"]
194    ENABLE = 0,
195    #[doc = "1: Disable DCXO wake up function"]
196    DISABLE = 1,
197}
198impl From<CLK_REQ_ENB_A> for bool {
199    #[inline(always)]
200    fn from(variant: CLK_REQ_ENB_A) -> Self {
201        variant as u8 != 0
202    }
203}
204impl CLK_REQ_ENB_R {
205    #[doc = "Get enumerated values variant"]
206    #[inline(always)]
207    pub const fn variant(&self) -> CLK_REQ_ENB_A {
208        match self.bits {
209            false => CLK_REQ_ENB_A::ENABLE,
210            true => CLK_REQ_ENB_A::DISABLE,
211        }
212    }
213    #[doc = "Enable DCXO wake up function"]
214    #[inline(always)]
215    pub fn is_enable(&self) -> bool {
216        *self == CLK_REQ_ENB_A::ENABLE
217    }
218    #[doc = "Disable DCXO wake up function"]
219    #[inline(always)]
220    pub fn is_disable(&self) -> bool {
221        *self == CLK_REQ_ENB_A::DISABLE
222    }
223}
224#[doc = "Field `clk_req_enb` writer - Clock REQ enable"]
225pub type CLK_REQ_ENB_W<'a, REG> = crate::BitWriter<'a, REG, CLK_REQ_ENB_A>;
226impl<'a, REG> CLK_REQ_ENB_W<'a, REG>
227where
228    REG: crate::Writable + crate::RegisterSpec,
229{
230    #[doc = "Enable DCXO wake up function"]
231    #[inline(always)]
232    pub fn enable(self) -> &'a mut crate::W<REG> {
233        self.variant(CLK_REQ_ENB_A::ENABLE)
234    }
235    #[doc = "Disable DCXO wake up function"]
236    #[inline(always)]
237    pub fn disable(self) -> &'a mut crate::W<REG> {
238        self.variant(CLK_REQ_ENB_A::DISABLE)
239    }
240}
241impl R {
242    #[doc = "Bit 0 - The related register configuration is necessary to ensure the reset debounce circuit has a stable clock source. The first time SoC starts up, by default, the reset debounce circuit of SoC uses 32K divided by RC16M. In power-off, software reads the related bit to ensure whether EXT32K is working normally, if it is normal, first switch the clock source of debounce circuit to EXT32K, then close RC16M. Without EXT32K scenario or external RTC scenario, software confirms firstly whether EXT32K is working normally before switching, or software does not close RC16M."]
243    #[inline(always)]
244    pub fn clk16m_rc_en(&self) -> CLK16M_RC_EN_R {
245        CLK16M_RC_EN_R::new((self.bits & 1) != 0)
246    }
247    #[doc = "Bit 1 - DCXO enable"]
248    #[inline(always)]
249    pub fn dcxo_en(&self) -> DCXO_EN_R {
250        DCXO_EN_R::new(((self.bits >> 1) & 1) != 0)
251    }
252    #[doc = "Bit 2 - For Debug Use Only.\n\nIt cannot configure to 0 in normal state."]
253    #[inline(always)]
254    pub fn rsto_dly_sel(&self) -> RSTO_DLY_SEL_R {
255        RSTO_DLY_SEL_R::new(((self.bits >> 2) & 1) != 0)
256    }
257    #[doc = "Bits 4:5 - DCXO rfclk enhance\n\nEnhance driving capacity of output OUT_RF_REFCLK, 0x0 for 5 pF, 0x1 for 10 pF, 0x2 for 15 pF, 0x3 for 20 pF."]
258    #[inline(always)]
259    pub fn dcxo_rfclk_enhance(&self) -> DCXO_RFCLK_ENHANCE_R {
260        DCXO_RFCLK_ENHANCE_R::new(((self.bits >> 4) & 3) as u8)
261    }
262    #[doc = "Bit 6 - Xtal mode enable signal, active high"]
263    #[inline(always)]
264    pub fn xtal_mode(&self) -> XTAL_MODE_R {
265        XTAL_MODE_R::new(((self.bits >> 6) & 1) != 0)
266    }
267    #[doc = "Bit 7 - DCXO LDO driving capacity signal, active high"]
268    #[inline(always)]
269    pub fn dcxo_ldo_inrushb(&self) -> DCXO_LDO_INRUSHB_R {
270        DCXO_LDO_INRUSHB_R::new(((self.bits >> 7) & 1) != 0)
271    }
272    #[doc = "Bits 8:12 - DCXO bandgap output voltage"]
273    #[inline(always)]
274    pub fn dcxo_bg(&self) -> DCXO_BG_R {
275        DCXO_BG_R::new(((self.bits >> 8) & 0x1f) as u8)
276    }
277    #[doc = "Bits 16:22 - DCXO cap array value\n\nThe capacity cell is 55 fF."]
278    #[inline(always)]
279    pub fn dcxo_trim(&self) -> DCXO_TRIM_R {
280        DCXO_TRIM_R::new(((self.bits >> 16) & 0x7f) as u8)
281    }
282    #[doc = "Bits 24:27 - DCXO current control value"]
283    #[inline(always)]
284    pub fn dcxo_ictrl(&self) -> DCXO_ICTRL_R {
285        DCXO_ICTRL_R::new(((self.bits >> 24) & 0x0f) as u8)
286    }
287    #[doc = "Bit 31 - Clock REQ enable"]
288    #[inline(always)]
289    pub fn clk_req_enb(&self) -> CLK_REQ_ENB_R {
290        CLK_REQ_ENB_R::new(((self.bits >> 31) & 1) != 0)
291    }
292}
293impl W {
294    #[doc = "Bit 0 - The related register configuration is necessary to ensure the reset debounce circuit has a stable clock source. The first time SoC starts up, by default, the reset debounce circuit of SoC uses 32K divided by RC16M. In power-off, software reads the related bit to ensure whether EXT32K is working normally, if it is normal, first switch the clock source of debounce circuit to EXT32K, then close RC16M. Without EXT32K scenario or external RTC scenario, software confirms firstly whether EXT32K is working normally before switching, or software does not close RC16M."]
295    #[inline(always)]
296    #[must_use]
297    pub fn clk16m_rc_en(&mut self) -> CLK16M_RC_EN_W<DCXO_CTRL_SPEC> {
298        CLK16M_RC_EN_W::new(self, 0)
299    }
300    #[doc = "Bit 1 - DCXO enable"]
301    #[inline(always)]
302    #[must_use]
303    pub fn dcxo_en(&mut self) -> DCXO_EN_W<DCXO_CTRL_SPEC> {
304        DCXO_EN_W::new(self, 1)
305    }
306    #[doc = "Bit 2 - For Debug Use Only.\n\nIt cannot configure to 0 in normal state."]
307    #[inline(always)]
308    #[must_use]
309    pub fn rsto_dly_sel(&mut self) -> RSTO_DLY_SEL_W<DCXO_CTRL_SPEC> {
310        RSTO_DLY_SEL_W::new(self, 2)
311    }
312    #[doc = "Bits 4:5 - DCXO rfclk enhance\n\nEnhance driving capacity of output OUT_RF_REFCLK, 0x0 for 5 pF, 0x1 for 10 pF, 0x2 for 15 pF, 0x3 for 20 pF."]
313    #[inline(always)]
314    #[must_use]
315    pub fn dcxo_rfclk_enhance(&mut self) -> DCXO_RFCLK_ENHANCE_W<DCXO_CTRL_SPEC> {
316        DCXO_RFCLK_ENHANCE_W::new(self, 4)
317    }
318    #[doc = "Bit 6 - Xtal mode enable signal, active high"]
319    #[inline(always)]
320    #[must_use]
321    pub fn xtal_mode(&mut self) -> XTAL_MODE_W<DCXO_CTRL_SPEC> {
322        XTAL_MODE_W::new(self, 6)
323    }
324    #[doc = "Bit 7 - DCXO LDO driving capacity signal, active high"]
325    #[inline(always)]
326    #[must_use]
327    pub fn dcxo_ldo_inrushb(&mut self) -> DCXO_LDO_INRUSHB_W<DCXO_CTRL_SPEC> {
328        DCXO_LDO_INRUSHB_W::new(self, 7)
329    }
330    #[doc = "Bits 8:12 - DCXO bandgap output voltage"]
331    #[inline(always)]
332    #[must_use]
333    pub fn dcxo_bg(&mut self) -> DCXO_BG_W<DCXO_CTRL_SPEC> {
334        DCXO_BG_W::new(self, 8)
335    }
336    #[doc = "Bits 16:22 - DCXO cap array value\n\nThe capacity cell is 55 fF."]
337    #[inline(always)]
338    #[must_use]
339    pub fn dcxo_trim(&mut self) -> DCXO_TRIM_W<DCXO_CTRL_SPEC> {
340        DCXO_TRIM_W::new(self, 16)
341    }
342    #[doc = "Bits 24:27 - DCXO current control value"]
343    #[inline(always)]
344    #[must_use]
345    pub fn dcxo_ictrl(&mut self) -> DCXO_ICTRL_W<DCXO_CTRL_SPEC> {
346        DCXO_ICTRL_W::new(self, 24)
347    }
348    #[doc = "Bit 31 - Clock REQ enable"]
349    #[inline(always)]
350    #[must_use]
351    pub fn clk_req_enb(&mut self) -> CLK_REQ_ENB_W<DCXO_CTRL_SPEC> {
352        CLK_REQ_ENB_W::new(self, 31)
353    }
354    #[doc = r" Writes raw bits to the register."]
355    #[doc = r""]
356    #[doc = r" # Safety"]
357    #[doc = r""]
358    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
359    #[inline(always)]
360    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
361        self.bits = bits;
362        self
363    }
364}
365#[doc = "DCXO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dcxo_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dcxo_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
366pub struct DCXO_CTRL_SPEC;
367impl crate::RegisterSpec for DCXO_CTRL_SPEC {
368    type Ux = u32;
369}
370#[doc = "`read()` method returns [`dcxo_ctrl::R`](R) reader structure"]
371impl crate::Readable for DCXO_CTRL_SPEC {}
372#[doc = "`write(|w| ..)` method takes [`dcxo_ctrl::W`](W) writer structure"]
373impl crate::Writable for DCXO_CTRL_SPEC {
374    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
375    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
376}
377#[doc = "`reset()` method sets dcxo_ctrl to value 0x883f_10f7"]
378impl crate::Resettable for DCXO_CTRL_SPEC {
379    const RESET_VALUE: Self::Ux = 0x883f_10f7;
380}
d1_pac/rtc/dcxo_ctrl.rs

d1_pac/rtc/
dcxo_ctrl.rs
