d1_pac/riscv_cfg/
riscv_sta_add1.rs

1#[doc = "Register `riscv_sta_add1` reader"]
2pub type R = crate::R<RISCV_STA_ADD1_SPEC>;
3#[doc = "Register `riscv_sta_add1` writer"]
4pub type W = crate::W<RISCV_STA_ADD1_SPEC>;
5#[doc = "Field `sta_add_h` reader - Start Address High 8-bit"]
6pub type STA_ADD_H_R = crate::FieldReader;
7#[doc = "Field `sta_add_h` writer - Start Address High 8-bit"]
8pub type STA_ADD_H_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9impl R {
10    #[doc = "Bits 0:7 - Start Address High 8-bit"]
11    #[inline(always)]
12    pub fn sta_add_h(&self) -> STA_ADD_H_R {
13        STA_ADD_H_R::new((self.bits & 0xff) as u8)
14    }
15}
16impl W {
17    #[doc = "Bits 0:7 - Start Address High 8-bit"]
18    #[inline(always)]
19    #[must_use]
20    pub fn sta_add_h(&mut self) -> STA_ADD_H_W<RISCV_STA_ADD1_SPEC> {
21        STA_ADD_H_W::new(self, 0)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "RISCV Start Address1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`riscv_sta_add1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`riscv_sta_add1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
35pub struct RISCV_STA_ADD1_SPEC;
36impl crate::RegisterSpec for RISCV_STA_ADD1_SPEC {
37    type Ux = u32;
38}
39#[doc = "`read()` method returns [`riscv_sta_add1::R`](R) reader structure"]
40impl crate::Readable for RISCV_STA_ADD1_SPEC {}
41#[doc = "`write(|w| ..)` method takes [`riscv_sta_add1::W`](W) writer structure"]
42impl crate::Writable for RISCV_STA_ADD1_SPEC {
43    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
44    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
45}
46#[doc = "`reset()` method sets riscv_sta_add1 to value 0"]
47impl crate::Resettable for RISCV_STA_ADD1_SPEC {
48    const RESET_VALUE: Self::Ux = 0;
49}
d1_pac/riscv_cfg/riscv_sta_add1.rs

d1_pac/riscv_cfg/
riscv_sta_add1.rs
