d1_pac/riscv_cfg/
retite_pc1.rs

1#[doc = "Register `retite_pc1` reader"]
2pub type R = crate::R<RETITE_PC1_SPEC>;
3#[doc = "Field `rt_pc_h` reader - Retire PC\\[39:32\\]"]
4pub type RT_PC_H_R = crate::FieldReader;
5#[doc = "Field `rt_sig` reader - Retire Signal"]
6pub type RT_SIG_R = crate::BitReader<RT_SIG_A>;
7#[doc = "Retire Signal\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum RT_SIG_A {
10    #[doc = "0: `0`"]
11    NOT_HAVE = 0,
12    #[doc = "1: `1`"]
13    HAVE = 1,
14}
15impl From<RT_SIG_A> for bool {
16    #[inline(always)]
17    fn from(variant: RT_SIG_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl RT_SIG_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> RT_SIG_A {
25        match self.bits {
26            false => RT_SIG_A::NOT_HAVE,
27            true => RT_SIG_A::HAVE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_not_have(&self) -> bool {
33        *self == RT_SIG_A::NOT_HAVE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_have(&self) -> bool {
38        *self == RT_SIG_A::HAVE
39    }
40}
41impl R {
42    #[doc = "Bits 0:7 - Retire PC\\[39:32\\]"]
43    #[inline(always)]
44    pub fn rt_pc_h(&self) -> RT_PC_H_R {
45        RT_PC_H_R::new((self.bits & 0xff) as u8)
46    }
47    #[doc = "Bit 31 - Retire Signal"]
48    #[inline(always)]
49    pub fn rt_sig(&self) -> RT_SIG_R {
50        RT_SIG_R::new(((self.bits >> 31) & 1) != 0)
51    }
52}
53#[doc = "Retire PC1 Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`retite_pc1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
54pub struct RETITE_PC1_SPEC;
55impl crate::RegisterSpec for RETITE_PC1_SPEC {
56    type Ux = u32;
57}
58#[doc = "`read()` method returns [`retite_pc1::R`](R) reader structure"]
59impl crate::Readable for RETITE_PC1_SPEC {}
60#[doc = "`reset()` method sets retite_pc1 to value 0"]
61impl crate::Resettable for RETITE_PC1_SPEC {
62    const RESET_VALUE: Self::Ux = 0;
63}
d1_pac/riscv_cfg/retite_pc1.rs

d1_pac/riscv_cfg/
retite_pc1.rs
