d1_pac/pwm/
ppr.rs

1#[doc = "Register `ppr%s` reader"]
2pub type R = crate::R<PPR_SPEC>;
3#[doc = "Register `ppr%s` writer"]
4pub type W = crate::W<PPR_SPEC>;
5#[doc = "Field `pwm_act_cycle` reader - Number of the active cycles in the PWM clock.\n\nN: N cycles"]
6pub type PWM_ACT_CYCLE_R = crate::FieldReader<u16>;
7#[doc = "Field `pwm_act_cycle` writer - Number of the active cycles in the PWM clock.\n\nN: N cycles"]
8pub type PWM_ACT_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `pwm_entire_cycle` reader - Number of the entire cycles in the PWM clock.\n\nN: N + 1 cycles"]
10pub type PWM_ENTIRE_CYCLE_R = crate::FieldReader<u16>;
11#[doc = "Field `pwm_entire_cycle` writer - Number of the entire cycles in the PWM clock.\n\nN: N + 1 cycles"]
12pub type PWM_ENTIRE_CYCLE_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
13impl R {
14    #[doc = "Bits 0:15 - Number of the active cycles in the PWM clock.\n\nN: N cycles"]
15    #[inline(always)]
16    pub fn pwm_act_cycle(&self) -> PWM_ACT_CYCLE_R {
17        PWM_ACT_CYCLE_R::new((self.bits & 0xffff) as u16)
18    }
19    #[doc = "Bits 16:31 - Number of the entire cycles in the PWM clock.\n\nN: N + 1 cycles"]
20    #[inline(always)]
21    pub fn pwm_entire_cycle(&self) -> PWM_ENTIRE_CYCLE_R {
22        PWM_ENTIRE_CYCLE_R::new(((self.bits >> 16) & 0xffff) as u16)
23    }
24}
25impl W {
26    #[doc = "Bits 0:15 - Number of the active cycles in the PWM clock.\n\nN: N cycles"]
27    #[inline(always)]
28    #[must_use]
29    pub fn pwm_act_cycle(&mut self) -> PWM_ACT_CYCLE_W<PPR_SPEC> {
30        PWM_ACT_CYCLE_W::new(self, 0)
31    }
32    #[doc = "Bits 16:31 - Number of the entire cycles in the PWM clock.\n\nN: N + 1 cycles"]
33    #[inline(always)]
34    #[must_use]
35    pub fn pwm_entire_cycle(&mut self) -> PWM_ENTIRE_CYCLE_W<PPR_SPEC> {
36        PWM_ENTIRE_CYCLE_W::new(self, 16)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "PWM Period Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ppr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ppr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct PPR_SPEC;
51impl crate::RegisterSpec for PPR_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`ppr::R`](R) reader structure"]
55impl crate::Readable for PPR_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`ppr::W`](W) writer structure"]
57impl crate::Writable for PPR_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets ppr%s to value 0"]
62impl crate::Resettable for PPR_SPEC {
63    const RESET_VALUE: Self::Ux = 0;
64}
d1_pac/pwm/ppr.rs

d1_pac/pwm/
ppr.rs
