1#[doc = "Register `pisr` reader"]
2pub type R = crate::R<PISR_SPEC>;
3#[doc = "Register `pisr` writer"]
4pub type W = crate::W<PISR_SPEC>;
5#[doc = "Field `pis[0-7]` reader - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
6pub type PIS_R = crate::BitReader<PIS_A>;
7#[doc = "PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum PIS_A {
10 #[doc = "0: `0`"]
11 NOT_PENDING = 0,
12 #[doc = "1: `1`"]
13 PENDING = 1,
14}
15impl From<PIS_A> for bool {
16 #[inline(always)]
17 fn from(variant: PIS_A) -> Self {
18 variant as u8 != 0
19 }
20}
21impl PIS_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> PIS_A {
25 match self.bits {
26 false => PIS_A::NOT_PENDING,
27 true => PIS_A::PENDING,
28 }
29 }
30 #[doc = "`0`"]
31 #[inline(always)]
32 pub fn is_not_pending(&self) -> bool {
33 *self == PIS_A::NOT_PENDING
34 }
35 #[doc = "`1`"]
36 #[inline(always)]
37 pub fn is_pending(&self) -> bool {
38 *self == PIS_A::PENDING
39 }
40}
41#[doc = "Field `pis[0-7]` writer - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
42pub type PIS_W<'a, REG> = crate::BitWriter1C<'a, REG, PIS_A>;
43impl<'a, REG> PIS_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "`0`"]
48 #[inline(always)]
49 pub fn not_pending(self) -> &'a mut crate::W<REG> {
50 self.variant(PIS_A::NOT_PENDING)
51 }
52 #[doc = "`1`"]
53 #[inline(always)]
54 pub fn pending(self) -> &'a mut crate::W<REG> {
55 self.variant(PIS_A::PENDING)
56 }
57}
58#[doc = "Field `pgis[0-3]` reader - PWM Group Interrupt Status"]
59pub type PGIS_R = crate::BitReader;
60#[doc = "Field `pgis[0-3]` writer - PWM Group Interrupt Status"]
61pub type PGIS_W<'a, REG> = crate::BitWriter1C<'a, REG>;
62impl R {
63 #[doc = "PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pis0` field"]
64 #[inline(always)]
65 pub fn pis(&self, n: u8) -> PIS_R {
66 #[allow(clippy::no_effect)]
67 [(); 8][n as usize];
68 PIS_R::new(((self.bits >> n) & 1) != 0)
69 }
70 #[doc = "Bit 0 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
71 #[inline(always)]
72 pub fn pis0(&self) -> PIS_R {
73 PIS_R::new((self.bits & 1) != 0)
74 }
75 #[doc = "Bit 1 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
76 #[inline(always)]
77 pub fn pis1(&self) -> PIS_R {
78 PIS_R::new(((self.bits >> 1) & 1) != 0)
79 }
80 #[doc = "Bit 2 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
81 #[inline(always)]
82 pub fn pis2(&self) -> PIS_R {
83 PIS_R::new(((self.bits >> 2) & 1) != 0)
84 }
85 #[doc = "Bit 3 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
86 #[inline(always)]
87 pub fn pis3(&self) -> PIS_R {
88 PIS_R::new(((self.bits >> 3) & 1) != 0)
89 }
90 #[doc = "Bit 4 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
91 #[inline(always)]
92 pub fn pis4(&self) -> PIS_R {
93 PIS_R::new(((self.bits >> 4) & 1) != 0)
94 }
95 #[doc = "Bit 5 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
96 #[inline(always)]
97 pub fn pis5(&self) -> PIS_R {
98 PIS_R::new(((self.bits >> 5) & 1) != 0)
99 }
100 #[doc = "Bit 6 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
101 #[inline(always)]
102 pub fn pis6(&self) -> PIS_R {
103 PIS_R::new(((self.bits >> 6) & 1) != 0)
104 }
105 #[doc = "Bit 7 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
106 #[inline(always)]
107 pub fn pis7(&self) -> PIS_R {
108 PIS_R::new(((self.bits >> 7) & 1) != 0)
109 }
110 #[doc = "PWM Group Interrupt Status\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pgis0` field"]
111 #[inline(always)]
112 pub fn pgis(&self, n: u8) -> PGIS_R {
113 #[allow(clippy::no_effect)]
114 [(); 4][n as usize];
115 PGIS_R::new(((self.bits >> (n + 16)) & 1) != 0)
116 }
117 #[doc = "Bit 16 - PWM Group Interrupt Status"]
118 #[inline(always)]
119 pub fn pgis0(&self) -> PGIS_R {
120 PGIS_R::new(((self.bits >> 16) & 1) != 0)
121 }
122 #[doc = "Bit 17 - PWM Group Interrupt Status"]
123 #[inline(always)]
124 pub fn pgis1(&self) -> PGIS_R {
125 PGIS_R::new(((self.bits >> 17) & 1) != 0)
126 }
127 #[doc = "Bit 18 - PWM Group Interrupt Status"]
128 #[inline(always)]
129 pub fn pgis2(&self) -> PGIS_R {
130 PGIS_R::new(((self.bits >> 18) & 1) != 0)
131 }
132 #[doc = "Bit 19 - PWM Group Interrupt Status"]
133 #[inline(always)]
134 pub fn pgis3(&self) -> PGIS_R {
135 PGIS_R::new(((self.bits >> 19) & 1) != 0)
136 }
137}
138impl W {
139 #[doc = "PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pis0` field"]
140 #[inline(always)]
141 #[must_use]
142 pub fn pis(&mut self, n: u8) -> PIS_W<PISR_SPEC> {
143 #[allow(clippy::no_effect)]
144 [(); 8][n as usize];
145 PIS_W::new(self, n)
146 }
147 #[doc = "Bit 0 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
148 #[inline(always)]
149 #[must_use]
150 pub fn pis0(&mut self) -> PIS_W<PISR_SPEC> {
151 PIS_W::new(self, 0)
152 }
153 #[doc = "Bit 1 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
154 #[inline(always)]
155 #[must_use]
156 pub fn pis1(&mut self) -> PIS_W<PISR_SPEC> {
157 PIS_W::new(self, 1)
158 }
159 #[doc = "Bit 2 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
160 #[inline(always)]
161 #[must_use]
162 pub fn pis2(&mut self) -> PIS_W<PISR_SPEC> {
163 PIS_W::new(self, 2)
164 }
165 #[doc = "Bit 3 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
166 #[inline(always)]
167 #[must_use]
168 pub fn pis3(&mut self) -> PIS_W<PISR_SPEC> {
169 PIS_W::new(self, 3)
170 }
171 #[doc = "Bit 4 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
172 #[inline(always)]
173 #[must_use]
174 pub fn pis4(&mut self) -> PIS_W<PISR_SPEC> {
175 PIS_W::new(self, 4)
176 }
177 #[doc = "Bit 5 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
178 #[inline(always)]
179 #[must_use]
180 pub fn pis5(&mut self) -> PIS_W<PISR_SPEC> {
181 PIS_W::new(self, 5)
182 }
183 #[doc = "Bit 6 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
184 #[inline(always)]
185 #[must_use]
186 pub fn pis6(&mut self) -> PIS_W<PISR_SPEC> {
187 PIS_W::new(self, 6)
188 }
189 #[doc = "Bit 7 - PWM Channel Interrupt Status\n\nWhen the PWM channel counter reaches the Entire Cycle Value, this bit is set 1 by hardware. Writing 1 to clear this bit.\n\nReads 0: PWM channel 0 interrupt is not pending.\n\nReads 1: PWM channel 0 interrupt is pending.\n\nWrites 0: No effect.\n\nWrites 1: Clear PWM channel 0 interrupt status."]
190 #[inline(always)]
191 #[must_use]
192 pub fn pis7(&mut self) -> PIS_W<PISR_SPEC> {
193 PIS_W::new(self, 7)
194 }
195 #[doc = "PWM Group Interrupt Status\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pgis0` field"]
196 #[inline(always)]
197 #[must_use]
198 pub fn pgis(&mut self, n: u8) -> PGIS_W<PISR_SPEC> {
199 #[allow(clippy::no_effect)]
200 [(); 4][n as usize];
201 PGIS_W::new(self, n + 16)
202 }
203 #[doc = "Bit 16 - PWM Group Interrupt Status"]
204 #[inline(always)]
205 #[must_use]
206 pub fn pgis0(&mut self) -> PGIS_W<PISR_SPEC> {
207 PGIS_W::new(self, 16)
208 }
209 #[doc = "Bit 17 - PWM Group Interrupt Status"]
210 #[inline(always)]
211 #[must_use]
212 pub fn pgis1(&mut self) -> PGIS_W<PISR_SPEC> {
213 PGIS_W::new(self, 17)
214 }
215 #[doc = "Bit 18 - PWM Group Interrupt Status"]
216 #[inline(always)]
217 #[must_use]
218 pub fn pgis2(&mut self) -> PGIS_W<PISR_SPEC> {
219 PGIS_W::new(self, 18)
220 }
221 #[doc = "Bit 19 - PWM Group Interrupt Status"]
222 #[inline(always)]
223 #[must_use]
224 pub fn pgis3(&mut self) -> PGIS_W<PISR_SPEC> {
225 PGIS_W::new(self, 19)
226 }
227 #[doc = r" Writes raw bits to the register."]
228 #[doc = r""]
229 #[doc = r" # Safety"]
230 #[doc = r""]
231 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
232 #[inline(always)]
233 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
234 self.bits = bits;
235 self
236 }
237}
238#[doc = "PWM IRQ Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pisr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pisr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
239pub struct PISR_SPEC;
240impl crate::RegisterSpec for PISR_SPEC {
241 type Ux = u32;
242}
243#[doc = "`read()` method returns [`pisr::R`](R) reader structure"]
244impl crate::Readable for PISR_SPEC {}
245#[doc = "`write(|w| ..)` method takes [`pisr::W`](W) writer structure"]
246impl crate::Writable for PISR_SPEC {
247 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
248 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x0001_0001;
249}
250#[doc = "`reset()` method sets pisr to value 0"]
251impl crate::Resettable for PISR_SPEC {
252 const RESET_VALUE: Self::Ux = 0;
253}