1#[doc = "Register `pier` reader"]
2pub type R = crate::R<PIER_SPEC>;
3#[doc = "Register `pier` writer"]
4pub type W = crate::W<PIER_SPEC>;
5#[doc = "Field `pcie[0-7]` reader - PWM Channel Interrupt Enable"]
6pub type PCIE_R = crate::BitReader<PCIE_A>;
7#[doc = "PWM Channel Interrupt Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum PCIE_A {
10 #[doc = "0: PWM Channel Interrupt Disable"]
11 DISABLE = 0,
12 #[doc = "1: PWM Channel Interrupt Enable"]
13 ENABLE = 1,
14}
15impl From<PCIE_A> for bool {
16 #[inline(always)]
17 fn from(variant: PCIE_A) -> Self {
18 variant as u8 != 0
19 }
20}
21impl PCIE_R {
22 #[doc = "Get enumerated values variant"]
23 #[inline(always)]
24 pub const fn variant(&self) -> PCIE_A {
25 match self.bits {
26 false => PCIE_A::DISABLE,
27 true => PCIE_A::ENABLE,
28 }
29 }
30 #[doc = "PWM Channel Interrupt Disable"]
31 #[inline(always)]
32 pub fn is_disable(&self) -> bool {
33 *self == PCIE_A::DISABLE
34 }
35 #[doc = "PWM Channel Interrupt Enable"]
36 #[inline(always)]
37 pub fn is_enable(&self) -> bool {
38 *self == PCIE_A::ENABLE
39 }
40}
41#[doc = "Field `pcie[0-7]` writer - PWM Channel Interrupt Enable"]
42pub type PCIE_W<'a, REG> = crate::BitWriter<'a, REG, PCIE_A>;
43impl<'a, REG> PCIE_W<'a, REG>
44where
45 REG: crate::Writable + crate::RegisterSpec,
46{
47 #[doc = "PWM Channel Interrupt Disable"]
48 #[inline(always)]
49 pub fn disable(self) -> &'a mut crate::W<REG> {
50 self.variant(PCIE_A::DISABLE)
51 }
52 #[doc = "PWM Channel Interrupt Enable"]
53 #[inline(always)]
54 pub fn enable(self) -> &'a mut crate::W<REG> {
55 self.variant(PCIE_A::ENABLE)
56 }
57}
58#[doc = "Field `pgie[0-3]` reader - PWM Group Interrupt Enable"]
59pub type PGIE_R = crate::BitReader<PGIE_A>;
60#[doc = "PWM Group Interrupt Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum PGIE_A {
63 #[doc = "0: Disable"]
64 DISABLE = 0,
65 #[doc = "1: Enable"]
66 ENABLE = 1,
67}
68impl From<PGIE_A> for bool {
69 #[inline(always)]
70 fn from(variant: PGIE_A) -> Self {
71 variant as u8 != 0
72 }
73}
74impl PGIE_R {
75 #[doc = "Get enumerated values variant"]
76 #[inline(always)]
77 pub const fn variant(&self) -> PGIE_A {
78 match self.bits {
79 false => PGIE_A::DISABLE,
80 true => PGIE_A::ENABLE,
81 }
82 }
83 #[doc = "Disable"]
84 #[inline(always)]
85 pub fn is_disable(&self) -> bool {
86 *self == PGIE_A::DISABLE
87 }
88 #[doc = "Enable"]
89 #[inline(always)]
90 pub fn is_enable(&self) -> bool {
91 *self == PGIE_A::ENABLE
92 }
93}
94#[doc = "Field `pgie[0-3]` writer - PWM Group Interrupt Enable"]
95pub type PGIE_W<'a, REG> = crate::BitWriter<'a, REG, PGIE_A>;
96impl<'a, REG> PGIE_W<'a, REG>
97where
98 REG: crate::Writable + crate::RegisterSpec,
99{
100 #[doc = "Disable"]
101 #[inline(always)]
102 pub fn disable(self) -> &'a mut crate::W<REG> {
103 self.variant(PGIE_A::DISABLE)
104 }
105 #[doc = "Enable"]
106 #[inline(always)]
107 pub fn enable(self) -> &'a mut crate::W<REG> {
108 self.variant(PGIE_A::ENABLE)
109 }
110}
111impl R {
112 #[doc = "PWM Channel Interrupt Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pcie0` field"]
113 #[inline(always)]
114 pub fn pcie(&self, n: u8) -> PCIE_R {
115 #[allow(clippy::no_effect)]
116 [(); 8][n as usize];
117 PCIE_R::new(((self.bits >> n) & 1) != 0)
118 }
119 #[doc = "Bit 0 - PWM Channel Interrupt Enable"]
120 #[inline(always)]
121 pub fn pcie0(&self) -> PCIE_R {
122 PCIE_R::new((self.bits & 1) != 0)
123 }
124 #[doc = "Bit 1 - PWM Channel Interrupt Enable"]
125 #[inline(always)]
126 pub fn pcie1(&self) -> PCIE_R {
127 PCIE_R::new(((self.bits >> 1) & 1) != 0)
128 }
129 #[doc = "Bit 2 - PWM Channel Interrupt Enable"]
130 #[inline(always)]
131 pub fn pcie2(&self) -> PCIE_R {
132 PCIE_R::new(((self.bits >> 2) & 1) != 0)
133 }
134 #[doc = "Bit 3 - PWM Channel Interrupt Enable"]
135 #[inline(always)]
136 pub fn pcie3(&self) -> PCIE_R {
137 PCIE_R::new(((self.bits >> 3) & 1) != 0)
138 }
139 #[doc = "Bit 4 - PWM Channel Interrupt Enable"]
140 #[inline(always)]
141 pub fn pcie4(&self) -> PCIE_R {
142 PCIE_R::new(((self.bits >> 4) & 1) != 0)
143 }
144 #[doc = "Bit 5 - PWM Channel Interrupt Enable"]
145 #[inline(always)]
146 pub fn pcie5(&self) -> PCIE_R {
147 PCIE_R::new(((self.bits >> 5) & 1) != 0)
148 }
149 #[doc = "Bit 6 - PWM Channel Interrupt Enable"]
150 #[inline(always)]
151 pub fn pcie6(&self) -> PCIE_R {
152 PCIE_R::new(((self.bits >> 6) & 1) != 0)
153 }
154 #[doc = "Bit 7 - PWM Channel Interrupt Enable"]
155 #[inline(always)]
156 pub fn pcie7(&self) -> PCIE_R {
157 PCIE_R::new(((self.bits >> 7) & 1) != 0)
158 }
159 #[doc = "PWM Group Interrupt Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pgie0` field"]
160 #[inline(always)]
161 pub fn pgie(&self, n: u8) -> PGIE_R {
162 #[allow(clippy::no_effect)]
163 [(); 4][n as usize];
164 PGIE_R::new(((self.bits >> (n + 16)) & 1) != 0)
165 }
166 #[doc = "Bit 16 - PWM Group Interrupt Enable"]
167 #[inline(always)]
168 pub fn pgie0(&self) -> PGIE_R {
169 PGIE_R::new(((self.bits >> 16) & 1) != 0)
170 }
171 #[doc = "Bit 17 - PWM Group Interrupt Enable"]
172 #[inline(always)]
173 pub fn pgie1(&self) -> PGIE_R {
174 PGIE_R::new(((self.bits >> 17) & 1) != 0)
175 }
176 #[doc = "Bit 18 - PWM Group Interrupt Enable"]
177 #[inline(always)]
178 pub fn pgie2(&self) -> PGIE_R {
179 PGIE_R::new(((self.bits >> 18) & 1) != 0)
180 }
181 #[doc = "Bit 19 - PWM Group Interrupt Enable"]
182 #[inline(always)]
183 pub fn pgie3(&self) -> PGIE_R {
184 PGIE_R::new(((self.bits >> 19) & 1) != 0)
185 }
186}
187impl W {
188 #[doc = "PWM Channel Interrupt Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pcie0` field"]
189 #[inline(always)]
190 #[must_use]
191 pub fn pcie(&mut self, n: u8) -> PCIE_W<PIER_SPEC> {
192 #[allow(clippy::no_effect)]
193 [(); 8][n as usize];
194 PCIE_W::new(self, n)
195 }
196 #[doc = "Bit 0 - PWM Channel Interrupt Enable"]
197 #[inline(always)]
198 #[must_use]
199 pub fn pcie0(&mut self) -> PCIE_W<PIER_SPEC> {
200 PCIE_W::new(self, 0)
201 }
202 #[doc = "Bit 1 - PWM Channel Interrupt Enable"]
203 #[inline(always)]
204 #[must_use]
205 pub fn pcie1(&mut self) -> PCIE_W<PIER_SPEC> {
206 PCIE_W::new(self, 1)
207 }
208 #[doc = "Bit 2 - PWM Channel Interrupt Enable"]
209 #[inline(always)]
210 #[must_use]
211 pub fn pcie2(&mut self) -> PCIE_W<PIER_SPEC> {
212 PCIE_W::new(self, 2)
213 }
214 #[doc = "Bit 3 - PWM Channel Interrupt Enable"]
215 #[inline(always)]
216 #[must_use]
217 pub fn pcie3(&mut self) -> PCIE_W<PIER_SPEC> {
218 PCIE_W::new(self, 3)
219 }
220 #[doc = "Bit 4 - PWM Channel Interrupt Enable"]
221 #[inline(always)]
222 #[must_use]
223 pub fn pcie4(&mut self) -> PCIE_W<PIER_SPEC> {
224 PCIE_W::new(self, 4)
225 }
226 #[doc = "Bit 5 - PWM Channel Interrupt Enable"]
227 #[inline(always)]
228 #[must_use]
229 pub fn pcie5(&mut self) -> PCIE_W<PIER_SPEC> {
230 PCIE_W::new(self, 5)
231 }
232 #[doc = "Bit 6 - PWM Channel Interrupt Enable"]
233 #[inline(always)]
234 #[must_use]
235 pub fn pcie6(&mut self) -> PCIE_W<PIER_SPEC> {
236 PCIE_W::new(self, 6)
237 }
238 #[doc = "Bit 7 - PWM Channel Interrupt Enable"]
239 #[inline(always)]
240 #[must_use]
241 pub fn pcie7(&mut self) -> PCIE_W<PIER_SPEC> {
242 PCIE_W::new(self, 7)
243 }
244 #[doc = "PWM Group Interrupt Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pgie0` field"]
245 #[inline(always)]
246 #[must_use]
247 pub fn pgie(&mut self, n: u8) -> PGIE_W<PIER_SPEC> {
248 #[allow(clippy::no_effect)]
249 [(); 4][n as usize];
250 PGIE_W::new(self, n + 16)
251 }
252 #[doc = "Bit 16 - PWM Group Interrupt Enable"]
253 #[inline(always)]
254 #[must_use]
255 pub fn pgie0(&mut self) -> PGIE_W<PIER_SPEC> {
256 PGIE_W::new(self, 16)
257 }
258 #[doc = "Bit 17 - PWM Group Interrupt Enable"]
259 #[inline(always)]
260 #[must_use]
261 pub fn pgie1(&mut self) -> PGIE_W<PIER_SPEC> {
262 PGIE_W::new(self, 17)
263 }
264 #[doc = "Bit 18 - PWM Group Interrupt Enable"]
265 #[inline(always)]
266 #[must_use]
267 pub fn pgie2(&mut self) -> PGIE_W<PIER_SPEC> {
268 PGIE_W::new(self, 18)
269 }
270 #[doc = "Bit 19 - PWM Group Interrupt Enable"]
271 #[inline(always)]
272 #[must_use]
273 pub fn pgie3(&mut self) -> PGIE_W<PIER_SPEC> {
274 PGIE_W::new(self, 19)
275 }
276 #[doc = r" Writes raw bits to the register."]
277 #[doc = r""]
278 #[doc = r" # Safety"]
279 #[doc = r""]
280 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
281 #[inline(always)]
282 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
283 self.bits = bits;
284 self
285 }
286}
287#[doc = "PWM IRQ Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pier::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pier::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
288pub struct PIER_SPEC;
289impl crate::RegisterSpec for PIER_SPEC {
290 type Ux = u32;
291}
292#[doc = "`read()` method returns [`pier::R`](R) reader structure"]
293impl crate::Readable for PIER_SPEC {}
294#[doc = "`write(|w| ..)` method takes [`pier::W`](W) writer structure"]
295impl crate::Writable for PIER_SPEC {
296 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
297 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
298}
299#[doc = "`reset()` method sets pier to value 0"]
300impl crate::Resettable for PIER_SPEC {
301 const RESET_VALUE: Self::Ux = 0;
302}