d1_pac/pwm/
pccr01.rs

1#[doc = "Register `pccr01` reader"]
2pub type R = crate::R<PCCR01_SPEC>;
3#[doc = "Register `pccr01` writer"]
4pub type W = crate::W<PCCR01_SPEC>;
5#[doc = "Field `pwm01_clk_div_m` reader - PWM01 Clock Divide M"]
6pub type PWM01_CLK_DIV_M_R = crate::FieldReader<PWM01_CLK_DIV_M_A>;
7#[doc = "PWM01 Clock Divide M\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PWM01_CLK_DIV_M_A {
11    #[doc = "0: /1"]
12    M1 = 0,
13    #[doc = "1: /2"]
14    M2 = 1,
15    #[doc = "2: /4"]
16    M4 = 2,
17    #[doc = "3: /8"]
18    M8 = 3,
19    #[doc = "4: /16"]
20    M16 = 4,
21    #[doc = "5: /32"]
22    M32 = 5,
23    #[doc = "6: /64"]
24    M64 = 6,
25    #[doc = "7: /128"]
26    M128 = 7,
27    #[doc = "8: /256"]
28    M256 = 8,
29}
30impl From<PWM01_CLK_DIV_M_A> for u8 {
31    #[inline(always)]
32    fn from(variant: PWM01_CLK_DIV_M_A) -> Self {
33        variant as _
34    }
35}
36impl crate::FieldSpec for PWM01_CLK_DIV_M_A {
37    type Ux = u8;
38}
39impl PWM01_CLK_DIV_M_R {
40    #[doc = "Get enumerated values variant"]
41    #[inline(always)]
42    pub const fn variant(&self) -> Option<PWM01_CLK_DIV_M_A> {
43        match self.bits {
44            0 => Some(PWM01_CLK_DIV_M_A::M1),
45            1 => Some(PWM01_CLK_DIV_M_A::M2),
46            2 => Some(PWM01_CLK_DIV_M_A::M4),
47            3 => Some(PWM01_CLK_DIV_M_A::M8),
48            4 => Some(PWM01_CLK_DIV_M_A::M16),
49            5 => Some(PWM01_CLK_DIV_M_A::M32),
50            6 => Some(PWM01_CLK_DIV_M_A::M64),
51            7 => Some(PWM01_CLK_DIV_M_A::M128),
52            8 => Some(PWM01_CLK_DIV_M_A::M256),
53            _ => None,
54        }
55    }
56    #[doc = "/1"]
57    #[inline(always)]
58    pub fn is_m1(&self) -> bool {
59        *self == PWM01_CLK_DIV_M_A::M1
60    }
61    #[doc = "/2"]
62    #[inline(always)]
63    pub fn is_m2(&self) -> bool {
64        *self == PWM01_CLK_DIV_M_A::M2
65    }
66    #[doc = "/4"]
67    #[inline(always)]
68    pub fn is_m4(&self) -> bool {
69        *self == PWM01_CLK_DIV_M_A::M4
70    }
71    #[doc = "/8"]
72    #[inline(always)]
73    pub fn is_m8(&self) -> bool {
74        *self == PWM01_CLK_DIV_M_A::M8
75    }
76    #[doc = "/16"]
77    #[inline(always)]
78    pub fn is_m16(&self) -> bool {
79        *self == PWM01_CLK_DIV_M_A::M16
80    }
81    #[doc = "/32"]
82    #[inline(always)]
83    pub fn is_m32(&self) -> bool {
84        *self == PWM01_CLK_DIV_M_A::M32
85    }
86    #[doc = "/64"]
87    #[inline(always)]
88    pub fn is_m64(&self) -> bool {
89        *self == PWM01_CLK_DIV_M_A::M64
90    }
91    #[doc = "/128"]
92    #[inline(always)]
93    pub fn is_m128(&self) -> bool {
94        *self == PWM01_CLK_DIV_M_A::M128
95    }
96    #[doc = "/256"]
97    #[inline(always)]
98    pub fn is_m256(&self) -> bool {
99        *self == PWM01_CLK_DIV_M_A::M256
100    }
101}
102#[doc = "Field `pwm01_clk_div_m` writer - PWM01 Clock Divide M"]
103pub type PWM01_CLK_DIV_M_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PWM01_CLK_DIV_M_A>;
104impl<'a, REG> PWM01_CLK_DIV_M_W<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107    REG::Ux: From<u8>,
108{
109    #[doc = "/1"]
110    #[inline(always)]
111    pub fn m1(self) -> &'a mut crate::W<REG> {
112        self.variant(PWM01_CLK_DIV_M_A::M1)
113    }
114    #[doc = "/2"]
115    #[inline(always)]
116    pub fn m2(self) -> &'a mut crate::W<REG> {
117        self.variant(PWM01_CLK_DIV_M_A::M2)
118    }
119    #[doc = "/4"]
120    #[inline(always)]
121    pub fn m4(self) -> &'a mut crate::W<REG> {
122        self.variant(PWM01_CLK_DIV_M_A::M4)
123    }
124    #[doc = "/8"]
125    #[inline(always)]
126    pub fn m8(self) -> &'a mut crate::W<REG> {
127        self.variant(PWM01_CLK_DIV_M_A::M8)
128    }
129    #[doc = "/16"]
130    #[inline(always)]
131    pub fn m16(self) -> &'a mut crate::W<REG> {
132        self.variant(PWM01_CLK_DIV_M_A::M16)
133    }
134    #[doc = "/32"]
135    #[inline(always)]
136    pub fn m32(self) -> &'a mut crate::W<REG> {
137        self.variant(PWM01_CLK_DIV_M_A::M32)
138    }
139    #[doc = "/64"]
140    #[inline(always)]
141    pub fn m64(self) -> &'a mut crate::W<REG> {
142        self.variant(PWM01_CLK_DIV_M_A::M64)
143    }
144    #[doc = "/128"]
145    #[inline(always)]
146    pub fn m128(self) -> &'a mut crate::W<REG> {
147        self.variant(PWM01_CLK_DIV_M_A::M128)
148    }
149    #[doc = "/256"]
150    #[inline(always)]
151    pub fn m256(self) -> &'a mut crate::W<REG> {
152        self.variant(PWM01_CLK_DIV_M_A::M256)
153    }
154}
155#[doc = "Field `pwm01_clk_src` reader - Select PWM01 Clock Source"]
156pub type PWM01_CLK_SRC_R = crate::FieldReader<PWM01_CLK_SRC_A>;
157#[doc = "Select PWM01 Clock Source\n\nValue on reset: 0"]
158#[derive(Clone, Copy, Debug, PartialEq, Eq)]
159#[repr(u8)]
160pub enum PWM01_CLK_SRC_A {
161    #[doc = "0: HOSC"]
162    HOSC = 0,
163    #[doc = "1: APB0"]
164    APB0 = 1,
165}
166impl From<PWM01_CLK_SRC_A> for u8 {
167    #[inline(always)]
168    fn from(variant: PWM01_CLK_SRC_A) -> Self {
169        variant as _
170    }
171}
172impl crate::FieldSpec for PWM01_CLK_SRC_A {
173    type Ux = u8;
174}
175impl PWM01_CLK_SRC_R {
176    #[doc = "Get enumerated values variant"]
177    #[inline(always)]
178    pub const fn variant(&self) -> Option<PWM01_CLK_SRC_A> {
179        match self.bits {
180            0 => Some(PWM01_CLK_SRC_A::HOSC),
181            1 => Some(PWM01_CLK_SRC_A::APB0),
182            _ => None,
183        }
184    }
185    #[doc = "HOSC"]
186    #[inline(always)]
187    pub fn is_hosc(&self) -> bool {
188        *self == PWM01_CLK_SRC_A::HOSC
189    }
190    #[doc = "APB0"]
191    #[inline(always)]
192    pub fn is_apb0(&self) -> bool {
193        *self == PWM01_CLK_SRC_A::APB0
194    }
195}
196#[doc = "Field `pwm01_clk_src` writer - Select PWM01 Clock Source"]
197pub type PWM01_CLK_SRC_W<'a, REG> = crate::FieldWriter<'a, REG, 2, PWM01_CLK_SRC_A>;
198impl<'a, REG> PWM01_CLK_SRC_W<'a, REG>
199where
200    REG: crate::Writable + crate::RegisterSpec,
201    REG::Ux: From<u8>,
202{
203    #[doc = "HOSC"]
204    #[inline(always)]
205    pub fn hosc(self) -> &'a mut crate::W<REG> {
206        self.variant(PWM01_CLK_SRC_A::HOSC)
207    }
208    #[doc = "APB0"]
209    #[inline(always)]
210    pub fn apb0(self) -> &'a mut crate::W<REG> {
211        self.variant(PWM01_CLK_SRC_A::APB0)
212    }
213}
214impl R {
215    #[doc = "Bits 0:3 - PWM01 Clock Divide M"]
216    #[inline(always)]
217    pub fn pwm01_clk_div_m(&self) -> PWM01_CLK_DIV_M_R {
218        PWM01_CLK_DIV_M_R::new((self.bits & 0x0f) as u8)
219    }
220    #[doc = "Bits 7:8 - Select PWM01 Clock Source"]
221    #[inline(always)]
222    pub fn pwm01_clk_src(&self) -> PWM01_CLK_SRC_R {
223        PWM01_CLK_SRC_R::new(((self.bits >> 7) & 3) as u8)
224    }
225}
226impl W {
227    #[doc = "Bits 0:3 - PWM01 Clock Divide M"]
228    #[inline(always)]
229    #[must_use]
230    pub fn pwm01_clk_div_m(&mut self) -> PWM01_CLK_DIV_M_W<PCCR01_SPEC> {
231        PWM01_CLK_DIV_M_W::new(self, 0)
232    }
233    #[doc = "Bits 7:8 - Select PWM01 Clock Source"]
234    #[inline(always)]
235    #[must_use]
236    pub fn pwm01_clk_src(&mut self) -> PWM01_CLK_SRC_W<PCCR01_SPEC> {
237        PWM01_CLK_SRC_W::new(self, 7)
238    }
239    #[doc = r" Writes raw bits to the register."]
240    #[doc = r""]
241    #[doc = r" # Safety"]
242    #[doc = r""]
243    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
244    #[inline(always)]
245    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
246        self.bits = bits;
247        self
248    }
249}
250#[doc = "PWM01 Clock Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pccr01::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pccr01::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
251pub struct PCCR01_SPEC;
252impl crate::RegisterSpec for PCCR01_SPEC {
253    type Ux = u32;
254}
255#[doc = "`read()` method returns [`pccr01::R`](R) reader structure"]
256impl crate::Readable for PCCR01_SPEC {}
257#[doc = "`write(|w| ..)` method takes [`pccr01::W`](W) writer structure"]
258impl crate::Writable for PCCR01_SPEC {
259    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
260    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
261}
262#[doc = "`reset()` method sets pccr01 to value 0"]
263impl crate::Resettable for PCCR01_SPEC {
264    const RESET_VALUE: Self::Ux = 0;
265}
d1_pac/pwm/pccr01.rs

d1_pac/pwm/
pccr01.rs
