d1_pac/pwm/
ccr.rs

1#[doc = "Register `ccr%s` reader"]
2pub type R = crate::R<CCR_SPEC>;
3#[doc = "Register `ccr%s` writer"]
4pub type W = crate::W<CCR_SPEC>;
5#[doc = "Field `capinv` reader - Inverse the signal input from capture channel before 16-bit counter of capture channel."]
6pub type CAPINV_R = crate::BitReader<CAPINV_A>;
7#[doc = "Inverse the signal input from capture channel before 16-bit counter of capture channel.\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum CAPINV_A {
10    #[doc = "0: not inverse"]
11    NOT_INVERSE = 0,
12    #[doc = "1: inverse"]
13    INVERSE = 1,
14}
15impl From<CAPINV_A> for bool {
16    #[inline(always)]
17    fn from(variant: CAPINV_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl CAPINV_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> CAPINV_A {
25        match self.bits {
26            false => CAPINV_A::NOT_INVERSE,
27            true => CAPINV_A::INVERSE,
28        }
29    }
30    #[doc = "not inverse"]
31    #[inline(always)]
32    pub fn is_not_inverse(&self) -> bool {
33        *self == CAPINV_A::NOT_INVERSE
34    }
35    #[doc = "inverse"]
36    #[inline(always)]
37    pub fn is_inverse(&self) -> bool {
38        *self == CAPINV_A::INVERSE
39    }
40}
41#[doc = "Field `capinv` writer - Inverse the signal input from capture channel before 16-bit counter of capture channel."]
42pub type CAPINV_W<'a, REG> = crate::BitWriter<'a, REG, CAPINV_A>;
43impl<'a, REG> CAPINV_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "not inverse"]
48    #[inline(always)]
49    pub fn not_inverse(self) -> &'a mut crate::W<REG> {
50        self.variant(CAPINV_A::NOT_INVERSE)
51    }
52    #[doc = "inverse"]
53    #[inline(always)]
54    pub fn inverse(self) -> &'a mut crate::W<REG> {
55        self.variant(CAPINV_A::INVERSE)
56    }
57}
58#[doc = "Field `cfte` reader - Falling edge capture trigger enable"]
59pub type CFTE_R = crate::BitReader;
60#[doc = "Field `cfte` writer - Falling edge capture trigger enable"]
61pub type CFTE_W<'a, REG> = crate::BitWriter<'a, REG>;
62#[doc = "Field `crte` reader - Rising edge capture trigger enable"]
63pub type CRTE_R = crate::BitReader;
64#[doc = "Field `crte` writer - Rising edge capture trigger enable"]
65pub type CRTE_W<'a, REG> = crate::BitWriter<'a, REG>;
66#[doc = "Field `cflf` reader - When the capture channel captures a falling edge, the current value of the 16-bit up-counter is latched to CFLR, and then this bit is set 1 by hardware.\n\nWrite 1 to clear this bit."]
67pub type CFLF_R = crate::BitReader;
68#[doc = "Field `cflf` writer - When the capture channel captures a falling edge, the current value of the 16-bit up-counter is latched to CFLR, and then this bit is set 1 by hardware.\n\nWrite 1 to clear this bit."]
69pub type CFLF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
70#[doc = "Field `crlf` reader - When the capture channel captures a rising edge, the current value of the 16-bit up-counter is latched to CRLR, and then this bit is set 1 by hardware.\n\nWrite 1 to clear this bit."]
71pub type CRLF_R = crate::BitReader;
72#[doc = "Field `crlf` writer - When the capture channel captures a rising edge, the current value of the 16-bit up-counter is latched to CRLR, and then this bit is set 1 by hardware.\n\nWrite 1 to clear this bit."]
73pub type CRLF_W<'a, REG> = crate::BitWriter1C<'a, REG>;
74impl R {
75    #[doc = "Bit 0 - Inverse the signal input from capture channel before 16-bit counter of capture channel."]
76    #[inline(always)]
77    pub fn capinv(&self) -> CAPINV_R {
78        CAPINV_R::new((self.bits & 1) != 0)
79    }
80    #[doc = "Bit 1 - Falling edge capture trigger enable"]
81    #[inline(always)]
82    pub fn cfte(&self) -> CFTE_R {
83        CFTE_R::new(((self.bits >> 1) & 1) != 0)
84    }
85    #[doc = "Bit 2 - Rising edge capture trigger enable"]
86    #[inline(always)]
87    pub fn crte(&self) -> CRTE_R {
88        CRTE_R::new(((self.bits >> 2) & 1) != 0)
89    }
90    #[doc = "Bit 3 - When the capture channel captures a falling edge, the current value of the 16-bit up-counter is latched to CFLR, and then this bit is set 1 by hardware.\n\nWrite 1 to clear this bit."]
91    #[inline(always)]
92    pub fn cflf(&self) -> CFLF_R {
93        CFLF_R::new(((self.bits >> 3) & 1) != 0)
94    }
95    #[doc = "Bit 4 - When the capture channel captures a rising edge, the current value of the 16-bit up-counter is latched to CRLR, and then this bit is set 1 by hardware.\n\nWrite 1 to clear this bit."]
96    #[inline(always)]
97    pub fn crlf(&self) -> CRLF_R {
98        CRLF_R::new(((self.bits >> 4) & 1) != 0)
99    }
100}
101impl W {
102    #[doc = "Bit 0 - Inverse the signal input from capture channel before 16-bit counter of capture channel."]
103    #[inline(always)]
104    #[must_use]
105    pub fn capinv(&mut self) -> CAPINV_W<CCR_SPEC> {
106        CAPINV_W::new(self, 0)
107    }
108    #[doc = "Bit 1 - Falling edge capture trigger enable"]
109    #[inline(always)]
110    #[must_use]
111    pub fn cfte(&mut self) -> CFTE_W<CCR_SPEC> {
112        CFTE_W::new(self, 1)
113    }
114    #[doc = "Bit 2 - Rising edge capture trigger enable"]
115    #[inline(always)]
116    #[must_use]
117    pub fn crte(&mut self) -> CRTE_W<CCR_SPEC> {
118        CRTE_W::new(self, 2)
119    }
120    #[doc = "Bit 3 - When the capture channel captures a falling edge, the current value of the 16-bit up-counter is latched to CFLR, and then this bit is set 1 by hardware.\n\nWrite 1 to clear this bit."]
121    #[inline(always)]
122    #[must_use]
123    pub fn cflf(&mut self) -> CFLF_W<CCR_SPEC> {
124        CFLF_W::new(self, 3)
125    }
126    #[doc = "Bit 4 - When the capture channel captures a rising edge, the current value of the 16-bit up-counter is latched to CRLR, and then this bit is set 1 by hardware.\n\nWrite 1 to clear this bit."]
127    #[inline(always)]
128    #[must_use]
129    pub fn crlf(&mut self) -> CRLF_W<CCR_SPEC> {
130        CRLF_W::new(self, 4)
131    }
132    #[doc = r" Writes raw bits to the register."]
133    #[doc = r""]
134    #[doc = r" # Safety"]
135    #[doc = r""]
136    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
137    #[inline(always)]
138    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
139        self.bits = bits;
140        self
141    }
142}
143#[doc = "Capture Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ccr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ccr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
144pub struct CCR_SPEC;
145impl crate::RegisterSpec for CCR_SPEC {
146    type Ux = u32;
147}
148#[doc = "`read()` method returns [`ccr::R`](R) reader structure"]
149impl crate::Readable for CCR_SPEC {}
150#[doc = "`write(|w| ..)` method takes [`ccr::W`](W) writer structure"]
151impl crate::Writable for CCR_SPEC {
152    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
153    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x18;
154}
155#[doc = "`reset()` method sets ccr%s to value 0"]
156impl crate::Resettable for CCR_SPEC {
157    const RESET_VALUE: Self::Ux = 0;
158}
d1_pac/pwm/ccr.rs

d1_pac/pwm/
ccr.rs
