d1_pac/ledc/
ledc_wait_time0_ctrl.rs1#[doc = "Register `ledc_wait_time0_ctrl` reader"]
2pub type R = crate::R<LEDC_WAIT_TIME0_CTRL_SPEC>;
3#[doc = "Register `ledc_wait_time0_ctrl` writer"]
4pub type W = crate::W<LEDC_WAIT_TIME0_CTRL_SPEC>;
5#[doc = "Field `total_wait_time0` reader - "]
6pub type TOTAL_WAIT_TIME0_R = crate::FieldReader;
7#[doc = "Field `total_wait_time0` writer - "]
8pub type TOTAL_WAIT_TIME0_W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
9#[doc = "Field `wait_tim0_en` reader - "]
10pub type WAIT_TIM0_EN_R = crate::BitReader<WAIT_TIM0_EN_A>;
11#[doc = "\n\nValue on reset: 0"]
12#[derive(Clone, Copy, Debug, PartialEq, Eq)]
13pub enum WAIT_TIM0_EN_A {
14 #[doc = "0: `0`"]
15 DISABLE = 0,
16 #[doc = "1: `1`"]
17 ENABLE = 1,
18}
19impl From<WAIT_TIM0_EN_A> for bool {
20 #[inline(always)]
21 fn from(variant: WAIT_TIM0_EN_A) -> Self {
22 variant as u8 != 0
23 }
24}
25impl WAIT_TIM0_EN_R {
26 #[doc = "Get enumerated values variant"]
27 #[inline(always)]
28 pub const fn variant(&self) -> WAIT_TIM0_EN_A {
29 match self.bits {
30 false => WAIT_TIM0_EN_A::DISABLE,
31 true => WAIT_TIM0_EN_A::ENABLE,
32 }
33 }
34 #[doc = "`0`"]
35 #[inline(always)]
36 pub fn is_disable(&self) -> bool {
37 *self == WAIT_TIM0_EN_A::DISABLE
38 }
39 #[doc = "`1`"]
40 #[inline(always)]
41 pub fn is_enable(&self) -> bool {
42 *self == WAIT_TIM0_EN_A::ENABLE
43 }
44}
45#[doc = "Field `wait_tim0_en` writer - "]
46pub type WAIT_TIM0_EN_W<'a, REG> = crate::BitWriter<'a, REG, WAIT_TIM0_EN_A>;
47impl<'a, REG> WAIT_TIM0_EN_W<'a, REG>
48where
49 REG: crate::Writable + crate::RegisterSpec,
50{
51 #[doc = "`0`"]
52 #[inline(always)]
53 pub fn disable(self) -> &'a mut crate::W<REG> {
54 self.variant(WAIT_TIM0_EN_A::DISABLE)
55 }
56 #[doc = "`1`"]
57 #[inline(always)]
58 pub fn enable(self) -> &'a mut crate::W<REG> {
59 self.variant(WAIT_TIM0_EN_A::ENABLE)
60 }
61}
62impl R {
63 #[doc = "Bits 0:7"]
64 #[inline(always)]
65 pub fn total_wait_time0(&self) -> TOTAL_WAIT_TIME0_R {
66 TOTAL_WAIT_TIME0_R::new((self.bits & 0xff) as u8)
67 }
68 #[doc = "Bit 8"]
69 #[inline(always)]
70 pub fn wait_tim0_en(&self) -> WAIT_TIM0_EN_R {
71 WAIT_TIM0_EN_R::new(((self.bits >> 8) & 1) != 0)
72 }
73}
74impl W {
75 #[doc = "Bits 0:7"]
76 #[inline(always)]
77 #[must_use]
78 pub fn total_wait_time0(&mut self) -> TOTAL_WAIT_TIME0_W<LEDC_WAIT_TIME0_CTRL_SPEC> {
79 TOTAL_WAIT_TIME0_W::new(self, 0)
80 }
81 #[doc = "Bit 8"]
82 #[inline(always)]
83 #[must_use]
84 pub fn wait_tim0_en(&mut self) -> WAIT_TIM0_EN_W<LEDC_WAIT_TIME0_CTRL_SPEC> {
85 WAIT_TIM0_EN_W::new(self, 8)
86 }
87 #[doc = r" Writes raw bits to the register."]
88 #[doc = r""]
89 #[doc = r" # Safety"]
90 #[doc = r""]
91 #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
92 #[inline(always)]
93 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
94 self.bits = bits;
95 self
96 }
97}
98#[doc = "LEDC Wait Time0 Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_wait_time0_ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_wait_time0_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct LEDC_WAIT_TIME0_CTRL_SPEC;
100impl crate::RegisterSpec for LEDC_WAIT_TIME0_CTRL_SPEC {
101 type Ux = u32;
102}
103#[doc = "`read()` method returns [`ledc_wait_time0_ctrl::R`](R) reader structure"]
104impl crate::Readable for LEDC_WAIT_TIME0_CTRL_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`ledc_wait_time0_ctrl::W`](W) writer structure"]
106impl crate::Writable for LEDC_WAIT_TIME0_CTRL_SPEC {
107 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
108 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
109}
110#[doc = "`reset()` method sets ledc_wait_time0_ctrl to value 0"]
111impl crate::Resettable for LEDC_WAIT_TIME0_CTRL_SPEC {
112 const RESET_VALUE: Self::Ux = 0;
113}