d1_pac/ledc/
ledc_int_sts.rs

1#[doc = "Register `ledc_int_sts` reader"]
2pub type R = crate::R<LEDC_INT_STS_SPEC>;
3#[doc = "Register `ledc_int_sts` writer"]
4pub type W = crate::W<LEDC_INT_STS_SPEC>;
5#[doc = "Field `lec_trans_finish_int` reader - "]
6pub type LEC_TRANS_FINISH_INT_R = crate::BitReader<LEC_TRANS_FINISH_INT_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum LEC_TRANS_FINISH_INT_A {
10    #[doc = "0: `0`"]
11    NOT_TRANS_COMPLETE = 0,
12    #[doc = "1: `1`"]
13    TRANS_COMPLETE = 1,
14}
15impl From<LEC_TRANS_FINISH_INT_A> for bool {
16    #[inline(always)]
17    fn from(variant: LEC_TRANS_FINISH_INT_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl LEC_TRANS_FINISH_INT_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> LEC_TRANS_FINISH_INT_A {
25        match self.bits {
26            false => LEC_TRANS_FINISH_INT_A::NOT_TRANS_COMPLETE,
27            true => LEC_TRANS_FINISH_INT_A::TRANS_COMPLETE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_not_trans_complete(&self) -> bool {
33        *self == LEC_TRANS_FINISH_INT_A::NOT_TRANS_COMPLETE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_trans_complete(&self) -> bool {
38        *self == LEC_TRANS_FINISH_INT_A::TRANS_COMPLETE
39    }
40}
41#[doc = "Field `lec_trans_finish_int` writer - "]
42pub type LEC_TRANS_FINISH_INT_W<'a, REG> = crate::BitWriter1C<'a, REG, LEC_TRANS_FINISH_INT_A>;
43impl<'a, REG> LEC_TRANS_FINISH_INT_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn not_trans_complete(self) -> &'a mut crate::W<REG> {
50        self.variant(LEC_TRANS_FINISH_INT_A::NOT_TRANS_COMPLETE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn trans_complete(self) -> &'a mut crate::W<REG> {
55        self.variant(LEC_TRANS_FINISH_INT_A::TRANS_COMPLETE)
56    }
57}
58#[doc = "Field `fifo_cpureq_int` reader - "]
59pub type FIFO_CPUREQ_INT_R = crate::BitReader<FIFO_CPUREQ_INT_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum FIFO_CPUREQ_INT_A {
63    #[doc = "0: `0`"]
64    NOT_REQUEST = 0,
65    #[doc = "1: `1`"]
66    REQUEST = 1,
67}
68impl From<FIFO_CPUREQ_INT_A> for bool {
69    #[inline(always)]
70    fn from(variant: FIFO_CPUREQ_INT_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl FIFO_CPUREQ_INT_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> FIFO_CPUREQ_INT_A {
78        match self.bits {
79            false => FIFO_CPUREQ_INT_A::NOT_REQUEST,
80            true => FIFO_CPUREQ_INT_A::REQUEST,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_not_request(&self) -> bool {
86        *self == FIFO_CPUREQ_INT_A::NOT_REQUEST
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_request(&self) -> bool {
91        *self == FIFO_CPUREQ_INT_A::REQUEST
92    }
93}
94#[doc = "Field `fifo_cpureq_int` writer - "]
95pub type FIFO_CPUREQ_INT_W<'a, REG> = crate::BitWriter1C<'a, REG, FIFO_CPUREQ_INT_A>;
96impl<'a, REG> FIFO_CPUREQ_INT_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn not_request(self) -> &'a mut crate::W<REG> {
103        self.variant(FIFO_CPUREQ_INT_A::NOT_REQUEST)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn request(self) -> &'a mut crate::W<REG> {
108        self.variant(FIFO_CPUREQ_INT_A::REQUEST)
109    }
110}
111#[doc = "Field `waitdata_timeout_int` reader - "]
112pub type WAITDATA_TIMEOUT_INT_R = crate::BitReader<WAITDATA_TIMEOUT_INT_A>;
113#[doc = "\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum WAITDATA_TIMEOUT_INT_A {
116    #[doc = "0: `0`"]
117    NOT_TIMEOUT = 0,
118    #[doc = "1: `1`"]
119    TIMEOUT = 1,
120}
121impl From<WAITDATA_TIMEOUT_INT_A> for bool {
122    #[inline(always)]
123    fn from(variant: WAITDATA_TIMEOUT_INT_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl WAITDATA_TIMEOUT_INT_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> WAITDATA_TIMEOUT_INT_A {
131        match self.bits {
132            false => WAITDATA_TIMEOUT_INT_A::NOT_TIMEOUT,
133            true => WAITDATA_TIMEOUT_INT_A::TIMEOUT,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_not_timeout(&self) -> bool {
139        *self == WAITDATA_TIMEOUT_INT_A::NOT_TIMEOUT
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_timeout(&self) -> bool {
144        *self == WAITDATA_TIMEOUT_INT_A::TIMEOUT
145    }
146}
147#[doc = "Field `waitdata_timeout_int` writer - "]
148pub type WAITDATA_TIMEOUT_INT_W<'a, REG> = crate::BitWriter1C<'a, REG, WAITDATA_TIMEOUT_INT_A>;
149impl<'a, REG> WAITDATA_TIMEOUT_INT_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn not_timeout(self) -> &'a mut crate::W<REG> {
156        self.variant(WAITDATA_TIMEOUT_INT_A::NOT_TIMEOUT)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn timeout(self) -> &'a mut crate::W<REG> {
161        self.variant(WAITDATA_TIMEOUT_INT_A::TIMEOUT)
162    }
163}
164#[doc = "Field `fifo_overflow_int` reader - "]
165pub type FIFO_OVERFLOW_INT_R = crate::BitReader<FIFO_OVERFLOW_INT_A>;
166#[doc = "\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum FIFO_OVERFLOW_INT_A {
169    #[doc = "0: `0`"]
170    NOT_OVERFLOW = 0,
171    #[doc = "1: `1`"]
172    OVERFLOW = 1,
173}
174impl From<FIFO_OVERFLOW_INT_A> for bool {
175    #[inline(always)]
176    fn from(variant: FIFO_OVERFLOW_INT_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl FIFO_OVERFLOW_INT_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> FIFO_OVERFLOW_INT_A {
184        match self.bits {
185            false => FIFO_OVERFLOW_INT_A::NOT_OVERFLOW,
186            true => FIFO_OVERFLOW_INT_A::OVERFLOW,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_not_overflow(&self) -> bool {
192        *self == FIFO_OVERFLOW_INT_A::NOT_OVERFLOW
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_overflow(&self) -> bool {
197        *self == FIFO_OVERFLOW_INT_A::OVERFLOW
198    }
199}
200#[doc = "Field `fifo_overflow_int` writer - "]
201pub type FIFO_OVERFLOW_INT_W<'a, REG> = crate::BitWriter1C<'a, REG, FIFO_OVERFLOW_INT_A>;
202impl<'a, REG> FIFO_OVERFLOW_INT_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn not_overflow(self) -> &'a mut crate::W<REG> {
209        self.variant(FIFO_OVERFLOW_INT_A::NOT_OVERFLOW)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn overflow(self) -> &'a mut crate::W<REG> {
214        self.variant(FIFO_OVERFLOW_INT_A::OVERFLOW)
215    }
216}
217#[doc = "Field `fifo_wlw` reader - "]
218pub type FIFO_WLW_R = crate::FieldReader;
219#[doc = "Field `fifo_full` reader - "]
220pub type FIFO_FULL_R = crate::BitReader;
221#[doc = "Field `fifo_empty` reader - "]
222pub type FIFO_EMPTY_R = crate::BitReader;
223impl R {
224    #[doc = "Bit 0"]
225    #[inline(always)]
226    pub fn lec_trans_finish_int(&self) -> LEC_TRANS_FINISH_INT_R {
227        LEC_TRANS_FINISH_INT_R::new((self.bits & 1) != 0)
228    }
229    #[doc = "Bit 1"]
230    #[inline(always)]
231    pub fn fifo_cpureq_int(&self) -> FIFO_CPUREQ_INT_R {
232        FIFO_CPUREQ_INT_R::new(((self.bits >> 1) & 1) != 0)
233    }
234    #[doc = "Bit 3"]
235    #[inline(always)]
236    pub fn waitdata_timeout_int(&self) -> WAITDATA_TIMEOUT_INT_R {
237        WAITDATA_TIMEOUT_INT_R::new(((self.bits >> 3) & 1) != 0)
238    }
239    #[doc = "Bit 4"]
240    #[inline(always)]
241    pub fn fifo_overflow_int(&self) -> FIFO_OVERFLOW_INT_R {
242        FIFO_OVERFLOW_INT_R::new(((self.bits >> 4) & 1) != 0)
243    }
244    #[doc = "Bits 10:15"]
245    #[inline(always)]
246    pub fn fifo_wlw(&self) -> FIFO_WLW_R {
247        FIFO_WLW_R::new(((self.bits >> 10) & 0x3f) as u8)
248    }
249    #[doc = "Bit 16"]
250    #[inline(always)]
251    pub fn fifo_full(&self) -> FIFO_FULL_R {
252        FIFO_FULL_R::new(((self.bits >> 16) & 1) != 0)
253    }
254    #[doc = "Bit 17"]
255    #[inline(always)]
256    pub fn fifo_empty(&self) -> FIFO_EMPTY_R {
257        FIFO_EMPTY_R::new(((self.bits >> 17) & 1) != 0)
258    }
259}
260impl W {
261    #[doc = "Bit 0"]
262    #[inline(always)]
263    #[must_use]
264    pub fn lec_trans_finish_int(&mut self) -> LEC_TRANS_FINISH_INT_W<LEDC_INT_STS_SPEC> {
265        LEC_TRANS_FINISH_INT_W::new(self, 0)
266    }
267    #[doc = "Bit 1"]
268    #[inline(always)]
269    #[must_use]
270    pub fn fifo_cpureq_int(&mut self) -> FIFO_CPUREQ_INT_W<LEDC_INT_STS_SPEC> {
271        FIFO_CPUREQ_INT_W::new(self, 1)
272    }
273    #[doc = "Bit 3"]
274    #[inline(always)]
275    #[must_use]
276    pub fn waitdata_timeout_int(&mut self) -> WAITDATA_TIMEOUT_INT_W<LEDC_INT_STS_SPEC> {
277        WAITDATA_TIMEOUT_INT_W::new(self, 3)
278    }
279    #[doc = "Bit 4"]
280    #[inline(always)]
281    #[must_use]
282    pub fn fifo_overflow_int(&mut self) -> FIFO_OVERFLOW_INT_W<LEDC_INT_STS_SPEC> {
283        FIFO_OVERFLOW_INT_W::new(self, 4)
284    }
285    #[doc = r" Writes raw bits to the register."]
286    #[doc = r""]
287    #[doc = r" # Safety"]
288    #[doc = r""]
289    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
290    #[inline(always)]
291    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
292        self.bits = bits;
293        self
294    }
295}
296#[doc = "LEDC Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_int_sts::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_int_sts::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
297pub struct LEDC_INT_STS_SPEC;
298impl crate::RegisterSpec for LEDC_INT_STS_SPEC {
299    type Ux = u32;
300}
301#[doc = "`read()` method returns [`ledc_int_sts::R`](R) reader structure"]
302impl crate::Readable for LEDC_INT_STS_SPEC {}
303#[doc = "`write(|w| ..)` method takes [`ledc_int_sts::W`](W) writer structure"]
304impl crate::Writable for LEDC_INT_STS_SPEC {
305    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
306    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0x1b;
307}
308#[doc = "`reset()` method sets ledc_int_sts to value 0"]
309impl crate::Resettable for LEDC_INT_STS_SPEC {
310    const RESET_VALUE: Self::Ux = 0;
311}
d1_pac/ledc/ledc_int_sts.rs

d1_pac/ledc/
ledc_int_sts.rs
