d1_pac/ledc/
ledc_int_ctrl.rs

1#[doc = "Register `ledc_int_ctrl` reader"]
2pub type R = crate::R<LEDC_INT_CTRL_SPEC>;
3#[doc = "Register `ledc_int_ctrl` writer"]
4pub type W = crate::W<LEDC_INT_CTRL_SPEC>;
5#[doc = "Field `led_trans_finish_int_en` reader - "]
6pub type LED_TRANS_FINISH_INT_EN_R = crate::BitReader<LED_TRANS_FINISH_INT_EN_A>;
7#[doc = "\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum LED_TRANS_FINISH_INT_EN_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<LED_TRANS_FINISH_INT_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: LED_TRANS_FINISH_INT_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl LED_TRANS_FINISH_INT_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> LED_TRANS_FINISH_INT_EN_A {
25        match self.bits {
26            false => LED_TRANS_FINISH_INT_EN_A::DISABLE,
27            true => LED_TRANS_FINISH_INT_EN_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == LED_TRANS_FINISH_INT_EN_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == LED_TRANS_FINISH_INT_EN_A::ENABLE
39    }
40}
41#[doc = "Field `led_trans_finish_int_en` writer - "]
42pub type LED_TRANS_FINISH_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, LED_TRANS_FINISH_INT_EN_A>;
43impl<'a, REG> LED_TRANS_FINISH_INT_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(LED_TRANS_FINISH_INT_EN_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(LED_TRANS_FINISH_INT_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `fifo_cpureq_int_en` reader - "]
59pub type FIFO_CPUREQ_INT_EN_R = crate::BitReader<FIFO_CPUREQ_INT_EN_A>;
60#[doc = "\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum FIFO_CPUREQ_INT_EN_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<FIFO_CPUREQ_INT_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: FIFO_CPUREQ_INT_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl FIFO_CPUREQ_INT_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> FIFO_CPUREQ_INT_EN_A {
78        match self.bits {
79            false => FIFO_CPUREQ_INT_EN_A::DISABLE,
80            true => FIFO_CPUREQ_INT_EN_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == FIFO_CPUREQ_INT_EN_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == FIFO_CPUREQ_INT_EN_A::ENABLE
92    }
93}
94#[doc = "Field `fifo_cpureq_int_en` writer - "]
95pub type FIFO_CPUREQ_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_CPUREQ_INT_EN_A>;
96impl<'a, REG> FIFO_CPUREQ_INT_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(FIFO_CPUREQ_INT_EN_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(FIFO_CPUREQ_INT_EN_A::ENABLE)
109    }
110}
111#[doc = "Field `waitdata_timeout_int_en` reader - "]
112pub type WAITDATA_TIMEOUT_INT_EN_R = crate::BitReader<WAITDATA_TIMEOUT_INT_EN_A>;
113#[doc = "\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum WAITDATA_TIMEOUT_INT_EN_A {
116    #[doc = "0: `0`"]
117    DISABLE = 0,
118    #[doc = "1: `1`"]
119    ENABLE = 1,
120}
121impl From<WAITDATA_TIMEOUT_INT_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: WAITDATA_TIMEOUT_INT_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl WAITDATA_TIMEOUT_INT_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> WAITDATA_TIMEOUT_INT_EN_A {
131        match self.bits {
132            false => WAITDATA_TIMEOUT_INT_EN_A::DISABLE,
133            true => WAITDATA_TIMEOUT_INT_EN_A::ENABLE,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == WAITDATA_TIMEOUT_INT_EN_A::DISABLE
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == WAITDATA_TIMEOUT_INT_EN_A::ENABLE
145    }
146}
147#[doc = "Field `waitdata_timeout_int_en` writer - "]
148pub type WAITDATA_TIMEOUT_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, WAITDATA_TIMEOUT_INT_EN_A>;
149impl<'a, REG> WAITDATA_TIMEOUT_INT_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(WAITDATA_TIMEOUT_INT_EN_A::DISABLE)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(WAITDATA_TIMEOUT_INT_EN_A::ENABLE)
162    }
163}
164#[doc = "Field `fifo_overflow_int_en` reader - "]
165pub type FIFO_OVERFLOW_INT_EN_R = crate::BitReader<FIFO_OVERFLOW_INT_EN_A>;
166#[doc = "\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum FIFO_OVERFLOW_INT_EN_A {
169    #[doc = "0: `0`"]
170    DISABLE = 0,
171    #[doc = "1: `1`"]
172    ENABLE = 1,
173}
174impl From<FIFO_OVERFLOW_INT_EN_A> for bool {
175    #[inline(always)]
176    fn from(variant: FIFO_OVERFLOW_INT_EN_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl FIFO_OVERFLOW_INT_EN_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> FIFO_OVERFLOW_INT_EN_A {
184        match self.bits {
185            false => FIFO_OVERFLOW_INT_EN_A::DISABLE,
186            true => FIFO_OVERFLOW_INT_EN_A::ENABLE,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_disable(&self) -> bool {
192        *self == FIFO_OVERFLOW_INT_EN_A::DISABLE
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_enable(&self) -> bool {
197        *self == FIFO_OVERFLOW_INT_EN_A::ENABLE
198    }
199}
200#[doc = "Field `fifo_overflow_int_en` writer - "]
201pub type FIFO_OVERFLOW_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, FIFO_OVERFLOW_INT_EN_A>;
202impl<'a, REG> FIFO_OVERFLOW_INT_EN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn disable(self) -> &'a mut crate::W<REG> {
209        self.variant(FIFO_OVERFLOW_INT_EN_A::DISABLE)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn enable(self) -> &'a mut crate::W<REG> {
214        self.variant(FIFO_OVERFLOW_INT_EN_A::ENABLE)
215    }
216}
217#[doc = "Field `global_int_en` reader - "]
218pub type GLOBAL_INT_EN_R = crate::BitReader<GLOBAL_INT_EN_A>;
219#[doc = "\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum GLOBAL_INT_EN_A {
222    #[doc = "0: `0`"]
223    DISABLE = 0,
224    #[doc = "1: `1`"]
225    ENABLE = 1,
226}
227impl From<GLOBAL_INT_EN_A> for bool {
228    #[inline(always)]
229    fn from(variant: GLOBAL_INT_EN_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl GLOBAL_INT_EN_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> GLOBAL_INT_EN_A {
237        match self.bits {
238            false => GLOBAL_INT_EN_A::DISABLE,
239            true => GLOBAL_INT_EN_A::ENABLE,
240        }
241    }
242    #[doc = "`0`"]
243    #[inline(always)]
244    pub fn is_disable(&self) -> bool {
245        *self == GLOBAL_INT_EN_A::DISABLE
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_enable(&self) -> bool {
250        *self == GLOBAL_INT_EN_A::ENABLE
251    }
252}
253#[doc = "Field `global_int_en` writer - "]
254pub type GLOBAL_INT_EN_W<'a, REG> = crate::BitWriter<'a, REG, GLOBAL_INT_EN_A>;
255impl<'a, REG> GLOBAL_INT_EN_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "`0`"]
260    #[inline(always)]
261    pub fn disable(self) -> &'a mut crate::W<REG> {
262        self.variant(GLOBAL_INT_EN_A::DISABLE)
263    }
264    #[doc = "`1`"]
265    #[inline(always)]
266    pub fn enable(self) -> &'a mut crate::W<REG> {
267        self.variant(GLOBAL_INT_EN_A::ENABLE)
268    }
269}
270impl R {
271    #[doc = "Bit 0"]
272    #[inline(always)]
273    pub fn led_trans_finish_int_en(&self) -> LED_TRANS_FINISH_INT_EN_R {
274        LED_TRANS_FINISH_INT_EN_R::new((self.bits & 1) != 0)
275    }
276    #[doc = "Bit 1"]
277    #[inline(always)]
278    pub fn fifo_cpureq_int_en(&self) -> FIFO_CPUREQ_INT_EN_R {
279        FIFO_CPUREQ_INT_EN_R::new(((self.bits >> 1) & 1) != 0)
280    }
281    #[doc = "Bit 3"]
282    #[inline(always)]
283    pub fn waitdata_timeout_int_en(&self) -> WAITDATA_TIMEOUT_INT_EN_R {
284        WAITDATA_TIMEOUT_INT_EN_R::new(((self.bits >> 3) & 1) != 0)
285    }
286    #[doc = "Bit 4"]
287    #[inline(always)]
288    pub fn fifo_overflow_int_en(&self) -> FIFO_OVERFLOW_INT_EN_R {
289        FIFO_OVERFLOW_INT_EN_R::new(((self.bits >> 4) & 1) != 0)
290    }
291    #[doc = "Bit 5"]
292    #[inline(always)]
293    pub fn global_int_en(&self) -> GLOBAL_INT_EN_R {
294        GLOBAL_INT_EN_R::new(((self.bits >> 5) & 1) != 0)
295    }
296}
297impl W {
298    #[doc = "Bit 0"]
299    #[inline(always)]
300    #[must_use]
301    pub fn led_trans_finish_int_en(&mut self) -> LED_TRANS_FINISH_INT_EN_W<LEDC_INT_CTRL_SPEC> {
302        LED_TRANS_FINISH_INT_EN_W::new(self, 0)
303    }
304    #[doc = "Bit 1"]
305    #[inline(always)]
306    #[must_use]
307    pub fn fifo_cpureq_int_en(&mut self) -> FIFO_CPUREQ_INT_EN_W<LEDC_INT_CTRL_SPEC> {
308        FIFO_CPUREQ_INT_EN_W::new(self, 1)
309    }
310    #[doc = "Bit 3"]
311    #[inline(always)]
312    #[must_use]
313    pub fn waitdata_timeout_int_en(&mut self) -> WAITDATA_TIMEOUT_INT_EN_W<LEDC_INT_CTRL_SPEC> {
314        WAITDATA_TIMEOUT_INT_EN_W::new(self, 3)
315    }
316    #[doc = "Bit 4"]
317    #[inline(always)]
318    #[must_use]
319    pub fn fifo_overflow_int_en(&mut self) -> FIFO_OVERFLOW_INT_EN_W<LEDC_INT_CTRL_SPEC> {
320        FIFO_OVERFLOW_INT_EN_W::new(self, 4)
321    }
322    #[doc = "Bit 5"]
323    #[inline(always)]
324    #[must_use]
325    pub fn global_int_en(&mut self) -> GLOBAL_INT_EN_W<LEDC_INT_CTRL_SPEC> {
326        GLOBAL_INT_EN_W::new(self, 5)
327    }
328    #[doc = r" Writes raw bits to the register."]
329    #[doc = r""]
330    #[doc = r" # Safety"]
331    #[doc = r""]
332    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
333    #[inline(always)]
334    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
335        self.bits = bits;
336        self
337    }
338}
339#[doc = "LEDC Interrupt Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ledc_int_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ledc_int_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
340pub struct LEDC_INT_CTRL_SPEC;
341impl crate::RegisterSpec for LEDC_INT_CTRL_SPEC {
342    type Ux = u32;
343}
344#[doc = "`read()` method returns [`ledc_int_ctrl::R`](R) reader structure"]
345impl crate::Readable for LEDC_INT_CTRL_SPEC {}
346#[doc = "`write(|w| ..)` method takes [`ledc_int_ctrl::W`](W) writer structure"]
347impl crate::Writable for LEDC_INT_CTRL_SPEC {
348    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
349    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
350}
351#[doc = "`reset()` method sets ledc_int_ctrl to value 0"]
352impl crate::Resettable for LEDC_INT_CTRL_SPEC {
353    const RESET_VALUE: Self::Ux = 0;
354}
d1_pac/ledc/ledc_int_ctrl.rs

d1_pac/ledc/
ledc_int_ctrl.rs
