d1_pac/iommu/
iommu_tlb_ivld_end_addr.rs

1#[doc = "Register `iommu_tlb_ivld_end_addr` reader"]
2pub type R = crate::R<IOMMU_TLB_IVLD_END_ADDR_SPEC>;
3#[doc = "Register `iommu_tlb_ivld_end_addr` writer"]
4pub type W = crate::W<IOMMU_TLB_IVLD_END_ADDR_SPEC>;
5#[doc = "Field `tlb_ivld_end_addr` reader - TLB invalid end address, 4 KB aligned."]
6pub type TLB_IVLD_END_ADDR_R = crate::FieldReader<u32>;
7#[doc = "Field `tlb_ivld_end_addr` writer - TLB invalid end address, 4 KB aligned."]
8pub type TLB_IVLD_END_ADDR_W<'a, REG> = crate::FieldWriter<'a, REG, 20, u32>;
9impl R {
10    #[doc = "Bits 12:31 - TLB invalid end address, 4 KB aligned."]
11    #[inline(always)]
12    pub fn tlb_ivld_end_addr(&self) -> TLB_IVLD_END_ADDR_R {
13        TLB_IVLD_END_ADDR_R::new((self.bits >> 12) & 0x000f_ffff)
14    }
15}
16impl W {
17    #[doc = "Bits 12:31 - TLB invalid end address, 4 KB aligned."]
18    #[inline(always)]
19    #[must_use]
20    pub fn tlb_ivld_end_addr(&mut self) -> TLB_IVLD_END_ADDR_W<IOMMU_TLB_IVLD_END_ADDR_SPEC> {
21        TLB_IVLD_END_ADDR_W::new(self, 12)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "IOMMU TLB Invalidation End Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_ivld_end_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_ivld_end_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
35pub struct IOMMU_TLB_IVLD_END_ADDR_SPEC;
36impl crate::RegisterSpec for IOMMU_TLB_IVLD_END_ADDR_SPEC {
37    type Ux = u32;
38}
39#[doc = "`read()` method returns [`iommu_tlb_ivld_end_addr::R`](R) reader structure"]
40impl crate::Readable for IOMMU_TLB_IVLD_END_ADDR_SPEC {}
41#[doc = "`write(|w| ..)` method takes [`iommu_tlb_ivld_end_addr::W`](W) writer structure"]
42impl crate::Writable for IOMMU_TLB_IVLD_END_ADDR_SPEC {
43    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
44    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
45}
46#[doc = "`reset()` method sets iommu_tlb_ivld_end_addr to value 0"]
47impl crate::Resettable for IOMMU_TLB_IVLD_END_ADDR_SPEC {
48    const RESET_VALUE: Self::Ux = 0;
49}
d1_pac/iommu/iommu_tlb_ivld_end_addr.rs

d1_pac/iommu/
iommu_tlb_ivld_end_addr.rs
