d1_pac/iommu/
iommu_tlb_enable.rs

1#[doc = "Register `iommu_tlb_enable` reader"]
2pub type R = crate::R<IOMMU_TLB_ENABLE_SPEC>;
3#[doc = "Register `iommu_tlb_enable` writer"]
4pub type W = crate::W<IOMMU_TLB_ENABLE_SPEC>;
5#[doc = "Field `micro_tlb_enable[0-6]` reader - Micro TLB\\[i\\] enable bit"]
6pub type MICRO_TLB_ENABLE_R = crate::BitReader<MICRO_TLB_ENABLE_A>;
7#[doc = "Micro TLB\\[i\\] enable bit\n\nValue on reset: 1"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum MICRO_TLB_ENABLE_A {
10    #[doc = "0: Disable"]
11    DISABLE = 0,
12    #[doc = "1: Enable"]
13    ENABLE = 1,
14}
15impl From<MICRO_TLB_ENABLE_A> for bool {
16    #[inline(always)]
17    fn from(variant: MICRO_TLB_ENABLE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl MICRO_TLB_ENABLE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> MICRO_TLB_ENABLE_A {
25        match self.bits {
26            false => MICRO_TLB_ENABLE_A::DISABLE,
27            true => MICRO_TLB_ENABLE_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == MICRO_TLB_ENABLE_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == MICRO_TLB_ENABLE_A::ENABLE
39    }
40}
41#[doc = "Field `micro_tlb_enable[0-6]` writer - Micro TLB\\[i\\] enable bit"]
42pub type MICRO_TLB_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, MICRO_TLB_ENABLE_A>;
43impl<'a, REG> MICRO_TLB_ENABLE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(MICRO_TLB_ENABLE_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(MICRO_TLB_ENABLE_A::ENABLE)
56    }
57}
58#[doc = "Field `macro_tlb_enable` reader - Macro TLB enable bit"]
59pub type MACRO_TLB_ENABLE_R = crate::BitReader<MACRO_TLB_ENABLE_A>;
60#[doc = "Macro TLB enable bit\n\nValue on reset: 1"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum MACRO_TLB_ENABLE_A {
63    #[doc = "0: Disable"]
64    DISABLE = 0,
65    #[doc = "1: Enable"]
66    ENABLE = 1,
67}
68impl From<MACRO_TLB_ENABLE_A> for bool {
69    #[inline(always)]
70    fn from(variant: MACRO_TLB_ENABLE_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl MACRO_TLB_ENABLE_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> MACRO_TLB_ENABLE_A {
78        match self.bits {
79            false => MACRO_TLB_ENABLE_A::DISABLE,
80            true => MACRO_TLB_ENABLE_A::ENABLE,
81        }
82    }
83    #[doc = "Disable"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == MACRO_TLB_ENABLE_A::DISABLE
87    }
88    #[doc = "Enable"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == MACRO_TLB_ENABLE_A::ENABLE
92    }
93}
94#[doc = "Field `macro_tlb_enable` writer - Macro TLB enable bit"]
95pub type MACRO_TLB_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, MACRO_TLB_ENABLE_A>;
96impl<'a, REG> MACRO_TLB_ENABLE_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Disable"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(MACRO_TLB_ENABLE_A::DISABLE)
104    }
105    #[doc = "Enable"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(MACRO_TLB_ENABLE_A::ENABLE)
109    }
110}
111#[doc = "Field `ptw_cache_enable` reader - PTW Cache enable bit"]
112pub type PTW_CACHE_ENABLE_R = crate::BitReader<PTW_CACHE_ENABLE_A>;
113#[doc = "PTW Cache enable bit\n\nValue on reset: 1"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum PTW_CACHE_ENABLE_A {
116    #[doc = "0: Disable"]
117    DISABLE = 0,
118    #[doc = "1: Enable"]
119    ENABLE = 1,
120}
121impl From<PTW_CACHE_ENABLE_A> for bool {
122    #[inline(always)]
123    fn from(variant: PTW_CACHE_ENABLE_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl PTW_CACHE_ENABLE_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> PTW_CACHE_ENABLE_A {
131        match self.bits {
132            false => PTW_CACHE_ENABLE_A::DISABLE,
133            true => PTW_CACHE_ENABLE_A::ENABLE,
134        }
135    }
136    #[doc = "Disable"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == PTW_CACHE_ENABLE_A::DISABLE
140    }
141    #[doc = "Enable"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == PTW_CACHE_ENABLE_A::ENABLE
145    }
146}
147#[doc = "Field `ptw_cache_enable` writer - PTW Cache enable bit"]
148pub type PTW_CACHE_ENABLE_W<'a, REG> = crate::BitWriter<'a, REG, PTW_CACHE_ENABLE_A>;
149impl<'a, REG> PTW_CACHE_ENABLE_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Disable"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(PTW_CACHE_ENABLE_A::DISABLE)
157    }
158    #[doc = "Enable"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(PTW_CACHE_ENABLE_A::ENABLE)
162    }
163}
164impl R {
165    #[doc = "Micro TLB\\[i\\] enable bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `micro_tlb0_enable` field"]
166    #[inline(always)]
167    pub fn micro_tlb_enable(&self, n: u8) -> MICRO_TLB_ENABLE_R {
168        #[allow(clippy::no_effect)]
169        [(); 7][n as usize];
170        MICRO_TLB_ENABLE_R::new(((self.bits >> n) & 1) != 0)
171    }
172    #[doc = "Bit 0 - Micro TLB\\[i\\] enable bit"]
173    #[inline(always)]
174    pub fn micro_tlb0_enable(&self) -> MICRO_TLB_ENABLE_R {
175        MICRO_TLB_ENABLE_R::new((self.bits & 1) != 0)
176    }
177    #[doc = "Bit 1 - Micro TLB\\[i\\] enable bit"]
178    #[inline(always)]
179    pub fn micro_tlb1_enable(&self) -> MICRO_TLB_ENABLE_R {
180        MICRO_TLB_ENABLE_R::new(((self.bits >> 1) & 1) != 0)
181    }
182    #[doc = "Bit 2 - Micro TLB\\[i\\] enable bit"]
183    #[inline(always)]
184    pub fn micro_tlb2_enable(&self) -> MICRO_TLB_ENABLE_R {
185        MICRO_TLB_ENABLE_R::new(((self.bits >> 2) & 1) != 0)
186    }
187    #[doc = "Bit 3 - Micro TLB\\[i\\] enable bit"]
188    #[inline(always)]
189    pub fn micro_tlb3_enable(&self) -> MICRO_TLB_ENABLE_R {
190        MICRO_TLB_ENABLE_R::new(((self.bits >> 3) & 1) != 0)
191    }
192    #[doc = "Bit 4 - Micro TLB\\[i\\] enable bit"]
193    #[inline(always)]
194    pub fn micro_tlb4_enable(&self) -> MICRO_TLB_ENABLE_R {
195        MICRO_TLB_ENABLE_R::new(((self.bits >> 4) & 1) != 0)
196    }
197    #[doc = "Bit 5 - Micro TLB\\[i\\] enable bit"]
198    #[inline(always)]
199    pub fn micro_tlb5_enable(&self) -> MICRO_TLB_ENABLE_R {
200        MICRO_TLB_ENABLE_R::new(((self.bits >> 5) & 1) != 0)
201    }
202    #[doc = "Bit 6 - Micro TLB\\[i\\] enable bit"]
203    #[inline(always)]
204    pub fn micro_tlb6_enable(&self) -> MICRO_TLB_ENABLE_R {
205        MICRO_TLB_ENABLE_R::new(((self.bits >> 6) & 1) != 0)
206    }
207    #[doc = "Bit 16 - Macro TLB enable bit"]
208    #[inline(always)]
209    pub fn macro_tlb_enable(&self) -> MACRO_TLB_ENABLE_R {
210        MACRO_TLB_ENABLE_R::new(((self.bits >> 16) & 1) != 0)
211    }
212    #[doc = "Bit 17 - PTW Cache enable bit"]
213    #[inline(always)]
214    pub fn ptw_cache_enable(&self) -> PTW_CACHE_ENABLE_R {
215        PTW_CACHE_ENABLE_R::new(((self.bits >> 17) & 1) != 0)
216    }
217}
218impl W {
219    #[doc = "Micro TLB\\[i\\] enable bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `micro_tlb0_enable` field"]
220    #[inline(always)]
221    #[must_use]
222    pub fn micro_tlb_enable(&mut self, n: u8) -> MICRO_TLB_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
223        #[allow(clippy::no_effect)]
224        [(); 7][n as usize];
225        MICRO_TLB_ENABLE_W::new(self, n)
226    }
227    #[doc = "Bit 0 - Micro TLB\\[i\\] enable bit"]
228    #[inline(always)]
229    #[must_use]
230    pub fn micro_tlb0_enable(&mut self) -> MICRO_TLB_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
231        MICRO_TLB_ENABLE_W::new(self, 0)
232    }
233    #[doc = "Bit 1 - Micro TLB\\[i\\] enable bit"]
234    #[inline(always)]
235    #[must_use]
236    pub fn micro_tlb1_enable(&mut self) -> MICRO_TLB_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
237        MICRO_TLB_ENABLE_W::new(self, 1)
238    }
239    #[doc = "Bit 2 - Micro TLB\\[i\\] enable bit"]
240    #[inline(always)]
241    #[must_use]
242    pub fn micro_tlb2_enable(&mut self) -> MICRO_TLB_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
243        MICRO_TLB_ENABLE_W::new(self, 2)
244    }
245    #[doc = "Bit 3 - Micro TLB\\[i\\] enable bit"]
246    #[inline(always)]
247    #[must_use]
248    pub fn micro_tlb3_enable(&mut self) -> MICRO_TLB_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
249        MICRO_TLB_ENABLE_W::new(self, 3)
250    }
251    #[doc = "Bit 4 - Micro TLB\\[i\\] enable bit"]
252    #[inline(always)]
253    #[must_use]
254    pub fn micro_tlb4_enable(&mut self) -> MICRO_TLB_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
255        MICRO_TLB_ENABLE_W::new(self, 4)
256    }
257    #[doc = "Bit 5 - Micro TLB\\[i\\] enable bit"]
258    #[inline(always)]
259    #[must_use]
260    pub fn micro_tlb5_enable(&mut self) -> MICRO_TLB_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
261        MICRO_TLB_ENABLE_W::new(self, 5)
262    }
263    #[doc = "Bit 6 - Micro TLB\\[i\\] enable bit"]
264    #[inline(always)]
265    #[must_use]
266    pub fn micro_tlb6_enable(&mut self) -> MICRO_TLB_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
267        MICRO_TLB_ENABLE_W::new(self, 6)
268    }
269    #[doc = "Bit 16 - Macro TLB enable bit"]
270    #[inline(always)]
271    #[must_use]
272    pub fn macro_tlb_enable(&mut self) -> MACRO_TLB_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
273        MACRO_TLB_ENABLE_W::new(self, 16)
274    }
275    #[doc = "Bit 17 - PTW Cache enable bit"]
276    #[inline(always)]
277    #[must_use]
278    pub fn ptw_cache_enable(&mut self) -> PTW_CACHE_ENABLE_W<IOMMU_TLB_ENABLE_SPEC> {
279        PTW_CACHE_ENABLE_W::new(self, 17)
280    }
281    #[doc = r" Writes raw bits to the register."]
282    #[doc = r""]
283    #[doc = r" # Safety"]
284    #[doc = r""]
285    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
286    #[inline(always)]
287    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
288        self.bits = bits;
289        self
290    }
291}
292#[doc = "IOMMU TLB Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_tlb_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_tlb_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
293pub struct IOMMU_TLB_ENABLE_SPEC;
294impl crate::RegisterSpec for IOMMU_TLB_ENABLE_SPEC {
295    type Ux = u32;
296}
297#[doc = "`read()` method returns [`iommu_tlb_enable::R`](R) reader structure"]
298impl crate::Readable for IOMMU_TLB_ENABLE_SPEC {}
299#[doc = "`write(|w| ..)` method takes [`iommu_tlb_enable::W`](W) writer structure"]
300impl crate::Writable for IOMMU_TLB_ENABLE_SPEC {
301    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
302    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
303}
304#[doc = "`reset()` method sets iommu_tlb_enable to value 0x0003_007f"]
305impl crate::Resettable for IOMMU_TLB_ENABLE_SPEC {
306    const RESET_VALUE: Self::Ux = 0x0003_007f;
307}
d1_pac/iommu/iommu_tlb_enable.rs

d1_pac/iommu/
iommu_tlb_enable.rs
