d1_pac/iommu/
iommu_reset.rs

1#[doc = "Register `iommu_reset` reader"]
2pub type R = crate::R<IOMMU_RESET_SPEC>;
3#[doc = "Register `iommu_reset` writer"]
4pub type W = crate::W<IOMMU_RESET_SPEC>;
5#[doc = "Field `m_rst[0-6]` reader - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
6pub type M_RST_R = crate::BitReader<M_RST_A>;
7#[doc = "Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually.\n\nValue on reset: 1"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum M_RST_A {
10    #[doc = "0: Set reset signal"]
11    SET = 0,
12    #[doc = "1: Release reset signal"]
13    R_ELEASE = 1,
14}
15impl From<M_RST_A> for bool {
16    #[inline(always)]
17    fn from(variant: M_RST_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl M_RST_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> M_RST_A {
25        match self.bits {
26            false => M_RST_A::SET,
27            true => M_RST_A::R_ELEASE,
28        }
29    }
30    #[doc = "Set reset signal"]
31    #[inline(always)]
32    pub fn is_set(&self) -> bool {
33        *self == M_RST_A::SET
34    }
35    #[doc = "Release reset signal"]
36    #[inline(always)]
37    pub fn is_r_elease(&self) -> bool {
38        *self == M_RST_A::R_ELEASE
39    }
40}
41#[doc = "Field `m_rst[0-6]` writer - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
42pub type M_RST_W<'a, REG> = crate::BitWriter<'a, REG, M_RST_A>;
43impl<'a, REG> M_RST_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Set reset signal"]
48    #[inline(always)]
49    pub fn set(self) -> &'a mut crate::W<REG> {
50        self.variant(M_RST_A::SET)
51    }
52    #[doc = "Release reset signal"]
53    #[inline(always)]
54    pub fn r_elease(self) -> &'a mut crate::W<REG> {
55        self.variant(M_RST_A::R_ELEASE)
56    }
57}
58#[doc = "Field `mtlb_rst` reader - Macrotlb Reset\n\nMacro TLB address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually."]
59pub type MTLB_RST_R = crate::BitReader<MTLB_RST_A>;
60#[doc = "Macrotlb Reset\n\nMacro TLB address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually.\n\nValue on reset: 1"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum MTLB_RST_A {
63    #[doc = "0: Set reset signal"]
64    SET = 0,
65    #[doc = "1: Release reset signal"]
66    R_ELEASE = 1,
67}
68impl From<MTLB_RST_A> for bool {
69    #[inline(always)]
70    fn from(variant: MTLB_RST_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl MTLB_RST_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> MTLB_RST_A {
78        match self.bits {
79            false => MTLB_RST_A::SET,
80            true => MTLB_RST_A::R_ELEASE,
81        }
82    }
83    #[doc = "Set reset signal"]
84    #[inline(always)]
85    pub fn is_set(&self) -> bool {
86        *self == MTLB_RST_A::SET
87    }
88    #[doc = "Release reset signal"]
89    #[inline(always)]
90    pub fn is_r_elease(&self) -> bool {
91        *self == MTLB_RST_A::R_ELEASE
92    }
93}
94#[doc = "Field `mtlb_rst` writer - Macrotlb Reset\n\nMacro TLB address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually."]
95pub type MTLB_RST_W<'a, REG> = crate::BitWriter<'a, REG, MTLB_RST_A>;
96impl<'a, REG> MTLB_RST_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Set reset signal"]
101    #[inline(always)]
102    pub fn set(self) -> &'a mut crate::W<REG> {
103        self.variant(MTLB_RST_A::SET)
104    }
105    #[doc = "Release reset signal"]
106    #[inline(always)]
107    pub fn r_elease(self) -> &'a mut crate::W<REG> {
108        self.variant(MTLB_RST_A::R_ELEASE)
109    }
110}
111#[doc = "Field `pc_rst` reader - PTW Cache Reset\n\nPTW Cache address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually."]
112pub type PC_RST_R = crate::BitReader<PC_RST_A>;
113#[doc = "PTW Cache Reset\n\nPTW Cache address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually.\n\nValue on reset: 1"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum PC_RST_A {
116    #[doc = "0: Set reset signal"]
117    SET = 0,
118    #[doc = "1: Release reset signal"]
119    R_ELEASE = 1,
120}
121impl From<PC_RST_A> for bool {
122    #[inline(always)]
123    fn from(variant: PC_RST_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl PC_RST_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> PC_RST_A {
131        match self.bits {
132            false => PC_RST_A::SET,
133            true => PC_RST_A::R_ELEASE,
134        }
135    }
136    #[doc = "Set reset signal"]
137    #[inline(always)]
138    pub fn is_set(&self) -> bool {
139        *self == PC_RST_A::SET
140    }
141    #[doc = "Release reset signal"]
142    #[inline(always)]
143    pub fn is_r_elease(&self) -> bool {
144        *self == PC_RST_A::R_ELEASE
145    }
146}
147#[doc = "Field `pc_rst` writer - PTW Cache Reset\n\nPTW Cache address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually."]
148pub type PC_RST_W<'a, REG> = crate::BitWriter<'a, REG, PC_RST_A>;
149impl<'a, REG> PC_RST_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Set reset signal"]
154    #[inline(always)]
155    pub fn set(self) -> &'a mut crate::W<REG> {
156        self.variant(PC_RST_A::SET)
157    }
158    #[doc = "Release reset signal"]
159    #[inline(always)]
160    pub fn r_elease(self) -> &'a mut crate::W<REG> {
161        self.variant(PC_RST_A::R_ELEASE)
162    }
163}
164#[doc = "Field `iommu_reset` reader - IOMMU Software Reset Switch、n\nBefore IOMMU software reset operation, ensure IOMMU never be opened; or all bus operations are completed; or DRAM and the peripherals have opened the corresponding switch, for shielding the effects of IOMMU reset."]
165pub type IOMMU_RESET_R = crate::BitReader<IOMMU_RESET_A>;
166#[doc = "IOMMU Software Reset Switch、n\nBefore IOMMU software reset operation, ensure IOMMU never be opened; or all bus operations are completed; or DRAM and the peripherals have opened the corresponding switch, for shielding the effects of IOMMU reset.\n\nValue on reset: 1"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum IOMMU_RESET_A {
169    #[doc = "0: Set reset signal"]
170    SET = 0,
171    #[doc = "1: Release reset signal"]
172    R_ELEASE = 1,
173}
174impl From<IOMMU_RESET_A> for bool {
175    #[inline(always)]
176    fn from(variant: IOMMU_RESET_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl IOMMU_RESET_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> IOMMU_RESET_A {
184        match self.bits {
185            false => IOMMU_RESET_A::SET,
186            true => IOMMU_RESET_A::R_ELEASE,
187        }
188    }
189    #[doc = "Set reset signal"]
190    #[inline(always)]
191    pub fn is_set(&self) -> bool {
192        *self == IOMMU_RESET_A::SET
193    }
194    #[doc = "Release reset signal"]
195    #[inline(always)]
196    pub fn is_r_elease(&self) -> bool {
197        *self == IOMMU_RESET_A::R_ELEASE
198    }
199}
200#[doc = "Field `iommu_reset` writer - IOMMU Software Reset Switch、n\nBefore IOMMU software reset operation, ensure IOMMU never be opened; or all bus operations are completed; or DRAM and the peripherals have opened the corresponding switch, for shielding the effects of IOMMU reset."]
201pub type IOMMU_RESET_W<'a, REG> = crate::BitWriter<'a, REG, IOMMU_RESET_A>;
202impl<'a, REG> IOMMU_RESET_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Set reset signal"]
207    #[inline(always)]
208    pub fn set(self) -> &'a mut crate::W<REG> {
209        self.variant(IOMMU_RESET_A::SET)
210    }
211    #[doc = "Release reset signal"]
212    #[inline(always)]
213    pub fn r_elease(self) -> &'a mut crate::W<REG> {
214        self.variant(IOMMU_RESET_A::R_ELEASE)
215    }
216}
217impl R {
218    #[doc = "Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `m0_rst` field"]
219    #[inline(always)]
220    pub fn m_rst(&self, n: u8) -> M_RST_R {
221        #[allow(clippy::no_effect)]
222        [(); 7][n as usize];
223        M_RST_R::new(((self.bits >> n) & 1) != 0)
224    }
225    #[doc = "Bit 0 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
226    #[inline(always)]
227    pub fn m0_rst(&self) -> M_RST_R {
228        M_RST_R::new((self.bits & 1) != 0)
229    }
230    #[doc = "Bit 1 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
231    #[inline(always)]
232    pub fn m1_rst(&self) -> M_RST_R {
233        M_RST_R::new(((self.bits >> 1) & 1) != 0)
234    }
235    #[doc = "Bit 2 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
236    #[inline(always)]
237    pub fn m2_rst(&self) -> M_RST_R {
238        M_RST_R::new(((self.bits >> 2) & 1) != 0)
239    }
240    #[doc = "Bit 3 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
241    #[inline(always)]
242    pub fn m3_rst(&self) -> M_RST_R {
243        M_RST_R::new(((self.bits >> 3) & 1) != 0)
244    }
245    #[doc = "Bit 4 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
246    #[inline(always)]
247    pub fn m4_rst(&self) -> M_RST_R {
248        M_RST_R::new(((self.bits >> 4) & 1) != 0)
249    }
250    #[doc = "Bit 5 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
251    #[inline(always)]
252    pub fn m5_rst(&self) -> M_RST_R {
253        M_RST_R::new(((self.bits >> 5) & 1) != 0)
254    }
255    #[doc = "Bit 6 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
256    #[inline(always)]
257    pub fn m6_rst(&self) -> M_RST_R {
258        M_RST_R::new(((self.bits >> 6) & 1) != 0)
259    }
260    #[doc = "Bit 16 - Macrotlb Reset\n\nMacro TLB address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually."]
261    #[inline(always)]
262    pub fn mtlb_rst(&self) -> MTLB_RST_R {
263        MTLB_RST_R::new(((self.bits >> 16) & 1) != 0)
264    }
265    #[doc = "Bit 17 - PTW Cache Reset\n\nPTW Cache address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually."]
266    #[inline(always)]
267    pub fn pc_rst(&self) -> PC_RST_R {
268        PC_RST_R::new(((self.bits >> 17) & 1) != 0)
269    }
270    #[doc = "Bit 31 - IOMMU Software Reset Switch、n\nBefore IOMMU software reset operation, ensure IOMMU never be opened; or all bus operations are completed; or DRAM and the peripherals have opened the corresponding switch, for shielding the effects of IOMMU reset."]
271    #[inline(always)]
272    pub fn iommu_reset(&self) -> IOMMU_RESET_R {
273        IOMMU_RESET_R::new(((self.bits >> 31) & 1) != 0)
274    }
275}
276impl W {
277    #[doc = "Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually.\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `m0_rst` field"]
278    #[inline(always)]
279    #[must_use]
280    pub fn m_rst(&mut self, n: u8) -> M_RST_W<IOMMU_RESET_SPEC> {
281        #[allow(clippy::no_effect)]
282        [(); 7][n as usize];
283        M_RST_W::new(self, n)
284    }
285    #[doc = "Bit 0 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
286    #[inline(always)]
287    #[must_use]
288    pub fn m0_rst(&mut self) -> M_RST_W<IOMMU_RESET_SPEC> {
289        M_RST_W::new(self, 0)
290    }
291    #[doc = "Bit 1 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
292    #[inline(always)]
293    #[must_use]
294    pub fn m1_rst(&mut self) -> M_RST_W<IOMMU_RESET_SPEC> {
295        M_RST_W::new(self, 1)
296    }
297    #[doc = "Bit 2 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
298    #[inline(always)]
299    #[must_use]
300    pub fn m2_rst(&mut self) -> M_RST_W<IOMMU_RESET_SPEC> {
301        M_RST_W::new(self, 2)
302    }
303    #[doc = "Bit 3 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
304    #[inline(always)]
305    #[must_use]
306    pub fn m3_rst(&mut self) -> M_RST_W<IOMMU_RESET_SPEC> {
307        M_RST_W::new(self, 3)
308    }
309    #[doc = "Bit 4 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
310    #[inline(always)]
311    #[must_use]
312    pub fn m4_rst(&mut self) -> M_RST_W<IOMMU_RESET_SPEC> {
313        M_RST_W::new(self, 4)
314    }
315    #[doc = "Bit 5 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
316    #[inline(always)]
317    #[must_use]
318    pub fn m5_rst(&mut self) -> M_RST_W<IOMMU_RESET_SPEC> {
319        M_RST_W::new(self, 5)
320    }
321    #[doc = "Bit 6 - Master\\[i\\] Reset\n\nMaster\\[i\\] address convert lane software reset switch.\n\nWhen Master\\[i\\] occurs abnormal, the bit is used to reset PTW Cache individually."]
322    #[inline(always)]
323    #[must_use]
324    pub fn m6_rst(&mut self) -> M_RST_W<IOMMU_RESET_SPEC> {
325        M_RST_W::new(self, 6)
326    }
327    #[doc = "Bit 16 - Macrotlb Reset\n\nMacro TLB address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually."]
328    #[inline(always)]
329    #[must_use]
330    pub fn mtlb_rst(&mut self) -> MTLB_RST_W<IOMMU_RESET_SPEC> {
331        MTLB_RST_W::new(self, 16)
332    }
333    #[doc = "Bit 17 - PTW Cache Reset\n\nPTW Cache address convert lane software reset switch.\n\nWhen PTW Cache occurs abnormal, the bit is used to reset PTW Cache individually."]
334    #[inline(always)]
335    #[must_use]
336    pub fn pc_rst(&mut self) -> PC_RST_W<IOMMU_RESET_SPEC> {
337        PC_RST_W::new(self, 17)
338    }
339    #[doc = "Bit 31 - IOMMU Software Reset Switch、n\nBefore IOMMU software reset operation, ensure IOMMU never be opened; or all bus operations are completed; or DRAM and the peripherals have opened the corresponding switch, for shielding the effects of IOMMU reset."]
340    #[inline(always)]
341    #[must_use]
342    pub fn iommu_reset(&mut self) -> IOMMU_RESET_W<IOMMU_RESET_SPEC> {
343        IOMMU_RESET_W::new(self, 31)
344    }
345    #[doc = r" Writes raw bits to the register."]
346    #[doc = r""]
347    #[doc = r" # Safety"]
348    #[doc = r""]
349    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
350    #[inline(always)]
351    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
352        self.bits = bits;
353        self
354    }
355}
356#[doc = "IOMMU Reset Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_reset::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_reset::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
357pub struct IOMMU_RESET_SPEC;
358impl crate::RegisterSpec for IOMMU_RESET_SPEC {
359    type Ux = u32;
360}
361#[doc = "`read()` method returns [`iommu_reset::R`](R) reader structure"]
362impl crate::Readable for IOMMU_RESET_SPEC {}
363#[doc = "`write(|w| ..)` method takes [`iommu_reset::W`](W) writer structure"]
364impl crate::Writable for IOMMU_RESET_SPEC {
365    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
366    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
367}
368#[doc = "`reset()` method sets iommu_reset to value 0x8003_007f"]
369impl crate::Resettable for IOMMU_RESET_SPEC {
370    const RESET_VALUE: Self::Ux = 0x8003_007f;
371}
d1_pac/iommu/iommu_reset.rs

d1_pac/iommu/
iommu_reset.rs
