d1_pac/iommu/
iommu_pc_ivld_sta_addr.rs

1#[doc = "Register `iommu_pc_ivld_sta_addr` reader"]
2pub type R = crate::R<IOMMU_PC_IVLD_STA_ADDR_SPEC>;
3#[doc = "Register `iommu_pc_ivld_sta_addr` writer"]
4pub type W = crate::W<IOMMU_PC_IVLD_STA_ADDR_SPEC>;
5#[doc = "Field `pc_ivld_sa` reader - PTW Cache invalid start address, 1 MB aligned."]
6pub type PC_IVLD_SA_R = crate::FieldReader<u16>;
7#[doc = "Field `pc_ivld_sa` writer - PTW Cache invalid start address, 1 MB aligned."]
8pub type PC_IVLD_SA_W<'a, REG> = crate::FieldWriter<'a, REG, 12, u16>;
9impl R {
10    #[doc = "Bits 20:31 - PTW Cache invalid start address, 1 MB aligned."]
11    #[inline(always)]
12    pub fn pc_ivld_sa(&self) -> PC_IVLD_SA_R {
13        PC_IVLD_SA_R::new(((self.bits >> 20) & 0x0fff) as u16)
14    }
15}
16impl W {
17    #[doc = "Bits 20:31 - PTW Cache invalid start address, 1 MB aligned."]
18    #[inline(always)]
19    #[must_use]
20    pub fn pc_ivld_sa(&mut self) -> PC_IVLD_SA_W<IOMMU_PC_IVLD_STA_ADDR_SPEC> {
21        PC_IVLD_SA_W::new(self, 20)
22    }
23    #[doc = r" Writes raw bits to the register."]
24    #[doc = r""]
25    #[doc = r" # Safety"]
26    #[doc = r""]
27    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
28    #[inline(always)]
29    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
30        self.bits = bits;
31        self
32    }
33}
34#[doc = "IOMMU PC Invalidation Start Address Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_pc_ivld_sta_addr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_pc_ivld_sta_addr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
35pub struct IOMMU_PC_IVLD_STA_ADDR_SPEC;
36impl crate::RegisterSpec for IOMMU_PC_IVLD_STA_ADDR_SPEC {
37    type Ux = u32;
38}
39#[doc = "`read()` method returns [`iommu_pc_ivld_sta_addr::R`](R) reader structure"]
40impl crate::Readable for IOMMU_PC_IVLD_STA_ADDR_SPEC {}
41#[doc = "`write(|w| ..)` method takes [`iommu_pc_ivld_sta_addr::W`](W) writer structure"]
42impl crate::Writable for IOMMU_PC_IVLD_STA_ADDR_SPEC {
43    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
44    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
45}
46#[doc = "`reset()` method sets iommu_pc_ivld_sta_addr to value 0"]
47impl crate::Resettable for IOMMU_PC_IVLD_STA_ADDR_SPEC {
48    const RESET_VALUE: Self::Ux = 0;
49}
d1_pac/iommu/iommu_pc_ivld_sta_addr.rs

d1_pac/iommu/
iommu_pc_ivld_sta_addr.rs
