d1_pac/iommu/
iommu_ooo_ctrl.rs

1#[doc = "Register `iommu_ooo_ctrl` reader"]
2pub type R = crate::R<IOMMU_OOO_CTRL_SPEC>;
3#[doc = "Register `iommu_ooo_ctrl` writer"]
4pub type W = crate::W<IOMMU_OOO_CTRL_SPEC>;
5#[doc = "Field `m_ooo_ctrl[0-6]` reader - Master\\[i\\] out-of-order control bit"]
6pub type M_OOO_CTRL_R = crate::BitReader<M_OOO_CTRL_A>;
7#[doc = "Master\\[i\\] out-of-order control bit\n\nValue on reset: 1"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum M_OOO_CTRL_A {
10    #[doc = "0: Disable out-of-order"]
11    DISABLE = 0,
12    #[doc = "1: Enable out-of-order"]
13    ENABLE = 1,
14}
15impl From<M_OOO_CTRL_A> for bool {
16    #[inline(always)]
17    fn from(variant: M_OOO_CTRL_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl M_OOO_CTRL_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> M_OOO_CTRL_A {
25        match self.bits {
26            false => M_OOO_CTRL_A::DISABLE,
27            true => M_OOO_CTRL_A::ENABLE,
28        }
29    }
30    #[doc = "Disable out-of-order"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == M_OOO_CTRL_A::DISABLE
34    }
35    #[doc = "Enable out-of-order"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == M_OOO_CTRL_A::ENABLE
39    }
40}
41#[doc = "Field `m_ooo_ctrl[0-6]` writer - Master\\[i\\] out-of-order control bit"]
42pub type M_OOO_CTRL_W<'a, REG> = crate::BitWriter<'a, REG, M_OOO_CTRL_A>;
43impl<'a, REG> M_OOO_CTRL_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable out-of-order"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(M_OOO_CTRL_A::DISABLE)
51    }
52    #[doc = "Enable out-of-order"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(M_OOO_CTRL_A::ENABLE)
56    }
57}
58impl R {
59    #[doc = "Master\\[i\\] out-of-order control bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `m0_ooo_ctrl` field"]
60    #[inline(always)]
61    pub fn m_ooo_ctrl(&self, n: u8) -> M_OOO_CTRL_R {
62        #[allow(clippy::no_effect)]
63        [(); 7][n as usize];
64        M_OOO_CTRL_R::new(((self.bits >> n) & 1) != 0)
65    }
66    #[doc = "Bit 0 - Master\\[i\\] out-of-order control bit"]
67    #[inline(always)]
68    pub fn m0_ooo_ctrl(&self) -> M_OOO_CTRL_R {
69        M_OOO_CTRL_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - Master\\[i\\] out-of-order control bit"]
72    #[inline(always)]
73    pub fn m1_ooo_ctrl(&self) -> M_OOO_CTRL_R {
74        M_OOO_CTRL_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2 - Master\\[i\\] out-of-order control bit"]
77    #[inline(always)]
78    pub fn m2_ooo_ctrl(&self) -> M_OOO_CTRL_R {
79        M_OOO_CTRL_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3 - Master\\[i\\] out-of-order control bit"]
82    #[inline(always)]
83    pub fn m3_ooo_ctrl(&self) -> M_OOO_CTRL_R {
84        M_OOO_CTRL_R::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4 - Master\\[i\\] out-of-order control bit"]
87    #[inline(always)]
88    pub fn m4_ooo_ctrl(&self) -> M_OOO_CTRL_R {
89        M_OOO_CTRL_R::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5 - Master\\[i\\] out-of-order control bit"]
92    #[inline(always)]
93    pub fn m5_ooo_ctrl(&self) -> M_OOO_CTRL_R {
94        M_OOO_CTRL_R::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 6 - Master\\[i\\] out-of-order control bit"]
97    #[inline(always)]
98    pub fn m6_ooo_ctrl(&self) -> M_OOO_CTRL_R {
99        M_OOO_CTRL_R::new(((self.bits >> 6) & 1) != 0)
100    }
101}
102impl W {
103    #[doc = "Master\\[i\\] out-of-order control bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `m0_ooo_ctrl` field"]
104    #[inline(always)]
105    #[must_use]
106    pub fn m_ooo_ctrl(&mut self, n: u8) -> M_OOO_CTRL_W<IOMMU_OOO_CTRL_SPEC> {
107        #[allow(clippy::no_effect)]
108        [(); 7][n as usize];
109        M_OOO_CTRL_W::new(self, n)
110    }
111    #[doc = "Bit 0 - Master\\[i\\] out-of-order control bit"]
112    #[inline(always)]
113    #[must_use]
114    pub fn m0_ooo_ctrl(&mut self) -> M_OOO_CTRL_W<IOMMU_OOO_CTRL_SPEC> {
115        M_OOO_CTRL_W::new(self, 0)
116    }
117    #[doc = "Bit 1 - Master\\[i\\] out-of-order control bit"]
118    #[inline(always)]
119    #[must_use]
120    pub fn m1_ooo_ctrl(&mut self) -> M_OOO_CTRL_W<IOMMU_OOO_CTRL_SPEC> {
121        M_OOO_CTRL_W::new(self, 1)
122    }
123    #[doc = "Bit 2 - Master\\[i\\] out-of-order control bit"]
124    #[inline(always)]
125    #[must_use]
126    pub fn m2_ooo_ctrl(&mut self) -> M_OOO_CTRL_W<IOMMU_OOO_CTRL_SPEC> {
127        M_OOO_CTRL_W::new(self, 2)
128    }
129    #[doc = "Bit 3 - Master\\[i\\] out-of-order control bit"]
130    #[inline(always)]
131    #[must_use]
132    pub fn m3_ooo_ctrl(&mut self) -> M_OOO_CTRL_W<IOMMU_OOO_CTRL_SPEC> {
133        M_OOO_CTRL_W::new(self, 3)
134    }
135    #[doc = "Bit 4 - Master\\[i\\] out-of-order control bit"]
136    #[inline(always)]
137    #[must_use]
138    pub fn m4_ooo_ctrl(&mut self) -> M_OOO_CTRL_W<IOMMU_OOO_CTRL_SPEC> {
139        M_OOO_CTRL_W::new(self, 4)
140    }
141    #[doc = "Bit 5 - Master\\[i\\] out-of-order control bit"]
142    #[inline(always)]
143    #[must_use]
144    pub fn m5_ooo_ctrl(&mut self) -> M_OOO_CTRL_W<IOMMU_OOO_CTRL_SPEC> {
145        M_OOO_CTRL_W::new(self, 5)
146    }
147    #[doc = "Bit 6 - Master\\[i\\] out-of-order control bit"]
148    #[inline(always)]
149    #[must_use]
150    pub fn m6_ooo_ctrl(&mut self) -> M_OOO_CTRL_W<IOMMU_OOO_CTRL_SPEC> {
151        M_OOO_CTRL_W::new(self, 6)
152    }
153    #[doc = r" Writes raw bits to the register."]
154    #[doc = r""]
155    #[doc = r" # Safety"]
156    #[doc = r""]
157    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
158    #[inline(always)]
159    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
160        self.bits = bits;
161        self
162    }
163}
164#[doc = "IOMMU Out of Order Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_ooo_ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_ooo_ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
165pub struct IOMMU_OOO_CTRL_SPEC;
166impl crate::RegisterSpec for IOMMU_OOO_CTRL_SPEC {
167    type Ux = u32;
168}
169#[doc = "`read()` method returns [`iommu_ooo_ctrl::R`](R) reader structure"]
170impl crate::Readable for IOMMU_OOO_CTRL_SPEC {}
171#[doc = "`write(|w| ..)` method takes [`iommu_ooo_ctrl::W`](W) writer structure"]
172impl crate::Writable for IOMMU_OOO_CTRL_SPEC {
173    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
174    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
175}
176#[doc = "`reset()` method sets iommu_ooo_ctrl to value 0x7f"]
177impl crate::Resettable for IOMMU_OOO_CTRL_SPEC {
178    const RESET_VALUE: Self::Ux = 0x7f;
179}
d1_pac/iommu/iommu_ooo_ctrl.rs

d1_pac/iommu/
iommu_ooo_ctrl.rs
