d1_pac/iommu/
iommu_lpg_int.rs

1#[doc = "Register `iommu_l%spg_int` reader"]
2pub type R = crate::R<IOMMU_LPG_INT_SPEC>;
3#[doc = "Field `master_int[0-6]` reader - Master\\[j\\] address switch causes L\\[i\\] page table to occur interrupt"]
4pub type MASTER_INT_R = crate::BitReader;
5#[doc = "Field `dbg_mode_int` reader - Debug mode address switch causes L\\[i\\] page table to occur interrupt"]
6pub type DBG_MODE_INT_R = crate::BitReader;
7impl R {
8    #[doc = "Master\\[j\\] address switch causes L\\[i\\] page table to occur interrupt\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `master0_int` field"]
9    #[inline(always)]
10    pub fn master_int(&self, n: u8) -> MASTER_INT_R {
11        #[allow(clippy::no_effect)]
12        [(); 7][n as usize];
13        MASTER_INT_R::new(((self.bits >> n) & 1) != 0)
14    }
15    #[doc = "Bit 0 - Master\\[j\\] address switch causes L\\[i\\] page table to occur interrupt"]
16    #[inline(always)]
17    pub fn master0_int(&self) -> MASTER_INT_R {
18        MASTER_INT_R::new((self.bits & 1) != 0)
19    }
20    #[doc = "Bit 1 - Master\\[j\\] address switch causes L\\[i\\] page table to occur interrupt"]
21    #[inline(always)]
22    pub fn master1_int(&self) -> MASTER_INT_R {
23        MASTER_INT_R::new(((self.bits >> 1) & 1) != 0)
24    }
25    #[doc = "Bit 2 - Master\\[j\\] address switch causes L\\[i\\] page table to occur interrupt"]
26    #[inline(always)]
27    pub fn master2_int(&self) -> MASTER_INT_R {
28        MASTER_INT_R::new(((self.bits >> 2) & 1) != 0)
29    }
30    #[doc = "Bit 3 - Master\\[j\\] address switch causes L\\[i\\] page table to occur interrupt"]
31    #[inline(always)]
32    pub fn master3_int(&self) -> MASTER_INT_R {
33        MASTER_INT_R::new(((self.bits >> 3) & 1) != 0)
34    }
35    #[doc = "Bit 4 - Master\\[j\\] address switch causes L\\[i\\] page table to occur interrupt"]
36    #[inline(always)]
37    pub fn master4_int(&self) -> MASTER_INT_R {
38        MASTER_INT_R::new(((self.bits >> 4) & 1) != 0)
39    }
40    #[doc = "Bit 5 - Master\\[j\\] address switch causes L\\[i\\] page table to occur interrupt"]
41    #[inline(always)]
42    pub fn master5_int(&self) -> MASTER_INT_R {
43        MASTER_INT_R::new(((self.bits >> 5) & 1) != 0)
44    }
45    #[doc = "Bit 6 - Master\\[j\\] address switch causes L\\[i\\] page table to occur interrupt"]
46    #[inline(always)]
47    pub fn master6_int(&self) -> MASTER_INT_R {
48        MASTER_INT_R::new(((self.bits >> 6) & 1) != 0)
49    }
50    #[doc = "Bit 31 - Debug mode address switch causes L\\[i\\] page table to occur interrupt"]
51    #[inline(always)]
52    pub fn dbg_mode_int(&self) -> DBG_MODE_INT_R {
53        DBG_MODE_INT_R::new(((self.bits >> 31) & 1) != 0)
54    }
55}
56#[doc = "IOMMU L\\[i\\] Page Table Interrupt Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_lpg_int::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
57pub struct IOMMU_LPG_INT_SPEC;
58impl crate::RegisterSpec for IOMMU_LPG_INT_SPEC {
59    type Ux = u32;
60}
61#[doc = "`read()` method returns [`iommu_lpg_int::R`](R) reader structure"]
62impl crate::Readable for IOMMU_LPG_INT_SPEC {}
63#[doc = "`reset()` method sets iommu_l%spg_int to value 0"]
64impl crate::Resettable for IOMMU_LPG_INT_SPEC {
65    const RESET_VALUE: Self::Ux = 0;
66}
d1_pac/iommu/iommu_lpg_int.rs

d1_pac/iommu/
iommu_lpg_int.rs
