d1_pac/iommu/
iommu_int_sta.rs

1#[doc = "Register `iommu_int_sta` reader"]
2pub type R = crate::R<IOMMU_INT_STA_SPEC>;
3#[doc = "Register `iommu_int_sta` writer"]
4pub type W = crate::W<IOMMU_INT_STA_SPEC>;
5#[doc = "Field `micro_tlb_invalid_sta[0-6]` reader - Micro TLB\\[i\\] permission invalid interrupt status bit"]
6pub type MICRO_TLB_INVALID_STA_R = crate::BitReader<MICRO_TLB_INVALID_STA_A>;
7#[doc = "Micro TLB\\[i\\] permission invalid interrupt status bit\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum MICRO_TLB_INVALID_STA_A {
10    #[doc = "0: Interrupt does not happen or interrupt is cleared"]
11    NOT_HAPPEN_OR_CLEARED = 0,
12    #[doc = "1: Interrupt happens"]
13    HAPPENS = 1,
14}
15impl From<MICRO_TLB_INVALID_STA_A> for bool {
16    #[inline(always)]
17    fn from(variant: MICRO_TLB_INVALID_STA_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl MICRO_TLB_INVALID_STA_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> MICRO_TLB_INVALID_STA_A {
25        match self.bits {
26            false => MICRO_TLB_INVALID_STA_A::NOT_HAPPEN_OR_CLEARED,
27            true => MICRO_TLB_INVALID_STA_A::HAPPENS,
28        }
29    }
30    #[doc = "Interrupt does not happen or interrupt is cleared"]
31    #[inline(always)]
32    pub fn is_not_happen_or_cleared(&self) -> bool {
33        *self == MICRO_TLB_INVALID_STA_A::NOT_HAPPEN_OR_CLEARED
34    }
35    #[doc = "Interrupt happens"]
36    #[inline(always)]
37    pub fn is_happens(&self) -> bool {
38        *self == MICRO_TLB_INVALID_STA_A::HAPPENS
39    }
40}
41#[doc = "Field `l_page_table_invalid_sta[0-1]` reader - Level\\[i\\] page table invalid interrupt status bit"]
42pub type L_PAGE_TABLE_INVALID_STA_R = crate::BitReader<L_PAGE_TABLE_INVALID_STA_A>;
43#[doc = "Level\\[i\\] page table invalid interrupt status bit\n\nValue on reset: 0"]
44#[derive(Clone, Copy, Debug, PartialEq, Eq)]
45pub enum L_PAGE_TABLE_INVALID_STA_A {
46    #[doc = "0: Interrupt does not happen or interrupt is cleared"]
47    NOT_HAPPEN_OR_CLEARED = 0,
48    #[doc = "1: Interrupt happens"]
49    HAPPENS = 1,
50}
51impl From<L_PAGE_TABLE_INVALID_STA_A> for bool {
52    #[inline(always)]
53    fn from(variant: L_PAGE_TABLE_INVALID_STA_A) -> Self {
54        variant as u8 != 0
55    }
56}
57impl L_PAGE_TABLE_INVALID_STA_R {
58    #[doc = "Get enumerated values variant"]
59    #[inline(always)]
60    pub const fn variant(&self) -> L_PAGE_TABLE_INVALID_STA_A {
61        match self.bits {
62            false => L_PAGE_TABLE_INVALID_STA_A::NOT_HAPPEN_OR_CLEARED,
63            true => L_PAGE_TABLE_INVALID_STA_A::HAPPENS,
64        }
65    }
66    #[doc = "Interrupt does not happen or interrupt is cleared"]
67    #[inline(always)]
68    pub fn is_not_happen_or_cleared(&self) -> bool {
69        *self == L_PAGE_TABLE_INVALID_STA_A::NOT_HAPPEN_OR_CLEARED
70    }
71    #[doc = "Interrupt happens"]
72    #[inline(always)]
73    pub fn is_happens(&self) -> bool {
74        *self == L_PAGE_TABLE_INVALID_STA_A::HAPPENS
75    }
76}
77impl R {
78    #[doc = "Micro TLB\\[i\\] permission invalid interrupt status bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `micro_tlb0_invalid_sta` field"]
79    #[inline(always)]
80    pub fn micro_tlb_invalid_sta(&self, n: u8) -> MICRO_TLB_INVALID_STA_R {
81        #[allow(clippy::no_effect)]
82        [(); 7][n as usize];
83        MICRO_TLB_INVALID_STA_R::new(((self.bits >> (n * 2)) & 1) != 0)
84    }
85    #[doc = "Bit 0 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
86    #[inline(always)]
87    pub fn micro_tlb0_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
88        MICRO_TLB_INVALID_STA_R::new((self.bits & 1) != 0)
89    }
90    #[doc = "Bit 2 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
91    #[inline(always)]
92    pub fn micro_tlb1_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
93        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 2) & 1) != 0)
94    }
95    #[doc = "Bit 4 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
96    #[inline(always)]
97    pub fn micro_tlb2_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
98        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 4) & 1) != 0)
99    }
100    #[doc = "Bit 6 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
101    #[inline(always)]
102    pub fn micro_tlb3_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
103        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 6) & 1) != 0)
104    }
105    #[doc = "Bit 8 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
106    #[inline(always)]
107    pub fn micro_tlb4_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
108        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 8) & 1) != 0)
109    }
110    #[doc = "Bit 10 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
111    #[inline(always)]
112    pub fn micro_tlb5_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
113        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 10) & 1) != 0)
114    }
115    #[doc = "Bit 12 - Micro TLB\\[i\\] permission invalid interrupt status bit"]
116    #[inline(always)]
117    pub fn micro_tlb6_invalid_sta(&self) -> MICRO_TLB_INVALID_STA_R {
118        MICRO_TLB_INVALID_STA_R::new(((self.bits >> 12) & 1) != 0)
119    }
120    #[doc = "Level\\[i\\] page table invalid interrupt status bit\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `l0_page_table_invalid_sta` field"]
121    #[inline(always)]
122    pub fn l_page_table_invalid_sta(&self, n: u8) -> L_PAGE_TABLE_INVALID_STA_R {
123        #[allow(clippy::no_effect)]
124        [(); 2][n as usize];
125        L_PAGE_TABLE_INVALID_STA_R::new(((self.bits >> (n + 16)) & 1) != 0)
126    }
127    #[doc = "Bit 16 - Level\\[i\\] page table invalid interrupt status bit"]
128    #[inline(always)]
129    pub fn l0_page_table_invalid_sta(&self) -> L_PAGE_TABLE_INVALID_STA_R {
130        L_PAGE_TABLE_INVALID_STA_R::new(((self.bits >> 16) & 1) != 0)
131    }
132    #[doc = "Bit 17 - Level\\[i\\] page table invalid interrupt status bit"]
133    #[inline(always)]
134    pub fn l1_page_table_invalid_sta(&self) -> L_PAGE_TABLE_INVALID_STA_R {
135        L_PAGE_TABLE_INVALID_STA_R::new(((self.bits >> 17) & 1) != 0)
136    }
137}
138impl W {
139    #[doc = r" Writes raw bits to the register."]
140    #[doc = r""]
141    #[doc = r" # Safety"]
142    #[doc = r""]
143    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
144    #[inline(always)]
145    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
146        self.bits = bits;
147        self
148    }
149}
150#[doc = "IOMMU Interrupt Status Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_sta::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_int_sta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
151pub struct IOMMU_INT_STA_SPEC;
152impl crate::RegisterSpec for IOMMU_INT_STA_SPEC {
153    type Ux = u32;
154}
155#[doc = "`read()` method returns [`iommu_int_sta::R`](R) reader structure"]
156impl crate::Readable for IOMMU_INT_STA_SPEC {}
157#[doc = "`write(|w| ..)` method takes [`iommu_int_sta::W`](W) writer structure"]
158impl crate::Writable for IOMMU_INT_STA_SPEC {
159    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
160    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
161}
162#[doc = "`reset()` method sets iommu_int_sta to value 0"]
163impl crate::Resettable for IOMMU_INT_STA_SPEC {
164    const RESET_VALUE: Self::Ux = 0;
165}
d1_pac/iommu/iommu_int_sta.rs

d1_pac/iommu/
iommu_int_sta.rs
