d1_pac/iommu/
iommu_int_err_addr_tlb.rs

1#[doc = "Register `iommu_int_err_addr_tlb%s` reader"]
2pub type R = crate::R<IOMMU_INT_ERR_ADDR_TLB_SPEC>;
3#[doc = "Field `int_err_addr` reader - Virtual address that caused Micro TLB\\[i\\] to interrupt"]
4pub type INT_ERR_ADDR_R = crate::FieldReader<u32>;
5impl R {
6    #[doc = "Bits 0:31 - Virtual address that caused Micro TLB\\[i\\] to interrupt"]
7    #[inline(always)]
8    pub fn int_err_addr(&self) -> INT_ERR_ADDR_R {
9        INT_ERR_ADDR_R::new(self.bits)
10    }
11}
12#[doc = "IOMMU Interrupt Error Address \\[i\\]\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_err_addr_tlb::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
13pub struct IOMMU_INT_ERR_ADDR_TLB_SPEC;
14impl crate::RegisterSpec for IOMMU_INT_ERR_ADDR_TLB_SPEC {
15    type Ux = u32;
16}
17#[doc = "`read()` method returns [`iommu_int_err_addr_tlb::R`](R) reader structure"]
18impl crate::Readable for IOMMU_INT_ERR_ADDR_TLB_SPEC {}
19#[doc = "`reset()` method sets iommu_int_err_addr_tlb%s to value 0"]
20impl crate::Resettable for IOMMU_INT_ERR_ADDR_TLB_SPEC {
21    const RESET_VALUE: Self::Ux = 0;
22}