d1_pac/iommu/
iommu_int_enable.rs

1#[doc = "Register `iommu_int_enable` reader"]
2pub type R = crate::R<IOMMU_INT_ENABLE_SPEC>;
3#[doc = "Register `iommu_int_enable` writer"]
4pub type W = crate::W<IOMMU_INT_ENABLE_SPEC>;
5#[doc = "Field `micro_tlb_invalid_en[0-6]` reader - Micro TLB\\[i\\] permission invalid interrupt enable"]
6pub type MICRO_TLB_INVALID_EN_R = crate::BitReader<MICRO_TLB_INVALID_EN_A>;
7#[doc = "Micro TLB\\[i\\] permission invalid interrupt enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum MICRO_TLB_INVALID_EN_A {
10    #[doc = "0: Mask interrupt"]
11    M_ASK = 0,
12    #[doc = "1: Enable interrupt"]
13    ENABLE = 1,
14}
15impl From<MICRO_TLB_INVALID_EN_A> for bool {
16    #[inline(always)]
17    fn from(variant: MICRO_TLB_INVALID_EN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl MICRO_TLB_INVALID_EN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> MICRO_TLB_INVALID_EN_A {
25        match self.bits {
26            false => MICRO_TLB_INVALID_EN_A::M_ASK,
27            true => MICRO_TLB_INVALID_EN_A::ENABLE,
28        }
29    }
30    #[doc = "Mask interrupt"]
31    #[inline(always)]
32    pub fn is_m_ask(&self) -> bool {
33        *self == MICRO_TLB_INVALID_EN_A::M_ASK
34    }
35    #[doc = "Enable interrupt"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == MICRO_TLB_INVALID_EN_A::ENABLE
39    }
40}
41#[doc = "Field `micro_tlb_invalid_en[0-6]` writer - Micro TLB\\[i\\] permission invalid interrupt enable"]
42pub type MICRO_TLB_INVALID_EN_W<'a, REG> = crate::BitWriter<'a, REG, MICRO_TLB_INVALID_EN_A>;
43impl<'a, REG> MICRO_TLB_INVALID_EN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Mask interrupt"]
48    #[inline(always)]
49    pub fn m_ask(self) -> &'a mut crate::W<REG> {
50        self.variant(MICRO_TLB_INVALID_EN_A::M_ASK)
51    }
52    #[doc = "Enable interrupt"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(MICRO_TLB_INVALID_EN_A::ENABLE)
56    }
57}
58#[doc = "Field `l_page_table_invalid_en[0-1]` reader - Level\\[i\\] page table invalid interrupt enable"]
59pub type L_PAGE_TABLE_INVALID_EN_R = crate::BitReader<L_PAGE_TABLE_INVALID_EN_A>;
60#[doc = "Level\\[i\\] page table invalid interrupt enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum L_PAGE_TABLE_INVALID_EN_A {
63    #[doc = "0: Mask interrupt"]
64    M_ASK = 0,
65    #[doc = "1: Enable interrupt"]
66    ENABLE = 1,
67}
68impl From<L_PAGE_TABLE_INVALID_EN_A> for bool {
69    #[inline(always)]
70    fn from(variant: L_PAGE_TABLE_INVALID_EN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl L_PAGE_TABLE_INVALID_EN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> L_PAGE_TABLE_INVALID_EN_A {
78        match self.bits {
79            false => L_PAGE_TABLE_INVALID_EN_A::M_ASK,
80            true => L_PAGE_TABLE_INVALID_EN_A::ENABLE,
81        }
82    }
83    #[doc = "Mask interrupt"]
84    #[inline(always)]
85    pub fn is_m_ask(&self) -> bool {
86        *self == L_PAGE_TABLE_INVALID_EN_A::M_ASK
87    }
88    #[doc = "Enable interrupt"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == L_PAGE_TABLE_INVALID_EN_A::ENABLE
92    }
93}
94#[doc = "Field `l_page_table_invalid_en[0-1]` writer - Level\\[i\\] page table invalid interrupt enable"]
95pub type L_PAGE_TABLE_INVALID_EN_W<'a, REG> = crate::BitWriter<'a, REG, L_PAGE_TABLE_INVALID_EN_A>;
96impl<'a, REG> L_PAGE_TABLE_INVALID_EN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "Mask interrupt"]
101    #[inline(always)]
102    pub fn m_ask(self) -> &'a mut crate::W<REG> {
103        self.variant(L_PAGE_TABLE_INVALID_EN_A::M_ASK)
104    }
105    #[doc = "Enable interrupt"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(L_PAGE_TABLE_INVALID_EN_A::ENABLE)
109    }
110}
111#[doc = "Field `dbg_pf_dram_iv_l1_pt_en` reader - Debug or Prefetch DRAM Invalid Level1 Page Table Enable"]
112pub type DBG_PF_DRAM_IV_L1_PT_EN_R = crate::BitReader<DBG_PF_DRAM_IV_L1_PT_EN_A>;
113#[doc = "Debug or Prefetch DRAM Invalid Level1 Page Table Enable\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum DBG_PF_DRAM_IV_L1_PT_EN_A {
116    #[doc = "0: Mask interrupt"]
117    M_ASK = 0,
118    #[doc = "1: Enable interrupt"]
119    ENABLE = 1,
120}
121impl From<DBG_PF_DRAM_IV_L1_PT_EN_A> for bool {
122    #[inline(always)]
123    fn from(variant: DBG_PF_DRAM_IV_L1_PT_EN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl DBG_PF_DRAM_IV_L1_PT_EN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> DBG_PF_DRAM_IV_L1_PT_EN_A {
131        match self.bits {
132            false => DBG_PF_DRAM_IV_L1_PT_EN_A::M_ASK,
133            true => DBG_PF_DRAM_IV_L1_PT_EN_A::ENABLE,
134        }
135    }
136    #[doc = "Mask interrupt"]
137    #[inline(always)]
138    pub fn is_m_ask(&self) -> bool {
139        *self == DBG_PF_DRAM_IV_L1_PT_EN_A::M_ASK
140    }
141    #[doc = "Enable interrupt"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == DBG_PF_DRAM_IV_L1_PT_EN_A::ENABLE
145    }
146}
147#[doc = "Field `dbg_pf_dram_iv_l1_pt_en` writer - Debug or Prefetch DRAM Invalid Level1 Page Table Enable"]
148pub type DBG_PF_DRAM_IV_L1_PT_EN_W<'a, REG> = crate::BitWriter<'a, REG, DBG_PF_DRAM_IV_L1_PT_EN_A>;
149impl<'a, REG> DBG_PF_DRAM_IV_L1_PT_EN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "Mask interrupt"]
154    #[inline(always)]
155    pub fn m_ask(self) -> &'a mut crate::W<REG> {
156        self.variant(DBG_PF_DRAM_IV_L1_PT_EN_A::M_ASK)
157    }
158    #[doc = "Enable interrupt"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(DBG_PF_DRAM_IV_L1_PT_EN_A::ENABLE)
162    }
163}
164#[doc = "Field `dbg_pf_pc_iv_l1_pt_en` reader - Debug or Prefetch PTW Cache Invalid Level1 Page Table Enable"]
165pub type DBG_PF_PC_IV_L1_PT_EN_R = crate::BitReader<DBG_PF_PC_IV_L1_PT_EN_A>;
166#[doc = "Debug or Prefetch PTW Cache Invalid Level1 Page Table Enable\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum DBG_PF_PC_IV_L1_PT_EN_A {
169    #[doc = "0: Mask interrupt"]
170    M_ASK = 0,
171    #[doc = "1: Enable interrupt"]
172    ENABLE = 1,
173}
174impl From<DBG_PF_PC_IV_L1_PT_EN_A> for bool {
175    #[inline(always)]
176    fn from(variant: DBG_PF_PC_IV_L1_PT_EN_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl DBG_PF_PC_IV_L1_PT_EN_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> DBG_PF_PC_IV_L1_PT_EN_A {
184        match self.bits {
185            false => DBG_PF_PC_IV_L1_PT_EN_A::M_ASK,
186            true => DBG_PF_PC_IV_L1_PT_EN_A::ENABLE,
187        }
188    }
189    #[doc = "Mask interrupt"]
190    #[inline(always)]
191    pub fn is_m_ask(&self) -> bool {
192        *self == DBG_PF_PC_IV_L1_PT_EN_A::M_ASK
193    }
194    #[doc = "Enable interrupt"]
195    #[inline(always)]
196    pub fn is_enable(&self) -> bool {
197        *self == DBG_PF_PC_IV_L1_PT_EN_A::ENABLE
198    }
199}
200#[doc = "Field `dbg_pf_pc_iv_l1_pt_en` writer - Debug or Prefetch PTW Cache Invalid Level1 Page Table Enable"]
201pub type DBG_PF_PC_IV_L1_PT_EN_W<'a, REG> = crate::BitWriter<'a, REG, DBG_PF_PC_IV_L1_PT_EN_A>;
202impl<'a, REG> DBG_PF_PC_IV_L1_PT_EN_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "Mask interrupt"]
207    #[inline(always)]
208    pub fn m_ask(self) -> &'a mut crate::W<REG> {
209        self.variant(DBG_PF_PC_IV_L1_PT_EN_A::M_ASK)
210    }
211    #[doc = "Enable interrupt"]
212    #[inline(always)]
213    pub fn enable(self) -> &'a mut crate::W<REG> {
214        self.variant(DBG_PF_PC_IV_L1_PT_EN_A::ENABLE)
215    }
216}
217#[doc = "Field `dbg_pf_l2_iv_pt_en` reader - Debug or Prefetch Invalid Page Table Enable"]
218pub type DBG_PF_L2_IV_PT_EN_R = crate::BitReader<DBG_PF_L2_IV_PT_EN_A>;
219#[doc = "Debug or Prefetch Invalid Page Table Enable\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221pub enum DBG_PF_L2_IV_PT_EN_A {
222    #[doc = "0: Mask interrupt"]
223    M_ASK = 0,
224    #[doc = "1: Enable interrupt"]
225    ENABLE = 1,
226}
227impl From<DBG_PF_L2_IV_PT_EN_A> for bool {
228    #[inline(always)]
229    fn from(variant: DBG_PF_L2_IV_PT_EN_A) -> Self {
230        variant as u8 != 0
231    }
232}
233impl DBG_PF_L2_IV_PT_EN_R {
234    #[doc = "Get enumerated values variant"]
235    #[inline(always)]
236    pub const fn variant(&self) -> DBG_PF_L2_IV_PT_EN_A {
237        match self.bits {
238            false => DBG_PF_L2_IV_PT_EN_A::M_ASK,
239            true => DBG_PF_L2_IV_PT_EN_A::ENABLE,
240        }
241    }
242    #[doc = "Mask interrupt"]
243    #[inline(always)]
244    pub fn is_m_ask(&self) -> bool {
245        *self == DBG_PF_L2_IV_PT_EN_A::M_ASK
246    }
247    #[doc = "Enable interrupt"]
248    #[inline(always)]
249    pub fn is_enable(&self) -> bool {
250        *self == DBG_PF_L2_IV_PT_EN_A::ENABLE
251    }
252}
253#[doc = "Field `dbg_pf_l2_iv_pt_en` writer - Debug or Prefetch Invalid Page Table Enable"]
254pub type DBG_PF_L2_IV_PT_EN_W<'a, REG> = crate::BitWriter<'a, REG, DBG_PF_L2_IV_PT_EN_A>;
255impl<'a, REG> DBG_PF_L2_IV_PT_EN_W<'a, REG>
256where
257    REG: crate::Writable + crate::RegisterSpec,
258{
259    #[doc = "Mask interrupt"]
260    #[inline(always)]
261    pub fn m_ask(self) -> &'a mut crate::W<REG> {
262        self.variant(DBG_PF_L2_IV_PT_EN_A::M_ASK)
263    }
264    #[doc = "Enable interrupt"]
265    #[inline(always)]
266    pub fn enable(self) -> &'a mut crate::W<REG> {
267        self.variant(DBG_PF_L2_IV_PT_EN_A::ENABLE)
268    }
269}
270impl R {
271    #[doc = "Micro TLB\\[i\\] permission invalid interrupt enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `micro_tlb0_invalid_en` field"]
272    #[inline(always)]
273    pub fn micro_tlb_invalid_en(&self, n: u8) -> MICRO_TLB_INVALID_EN_R {
274        #[allow(clippy::no_effect)]
275        [(); 7][n as usize];
276        MICRO_TLB_INVALID_EN_R::new(((self.bits >> (n * 2)) & 1) != 0)
277    }
278    #[doc = "Bit 0 - Micro TLB\\[i\\] permission invalid interrupt enable"]
279    #[inline(always)]
280    pub fn micro_tlb0_invalid_en(&self) -> MICRO_TLB_INVALID_EN_R {
281        MICRO_TLB_INVALID_EN_R::new((self.bits & 1) != 0)
282    }
283    #[doc = "Bit 2 - Micro TLB\\[i\\] permission invalid interrupt enable"]
284    #[inline(always)]
285    pub fn micro_tlb1_invalid_en(&self) -> MICRO_TLB_INVALID_EN_R {
286        MICRO_TLB_INVALID_EN_R::new(((self.bits >> 2) & 1) != 0)
287    }
288    #[doc = "Bit 4 - Micro TLB\\[i\\] permission invalid interrupt enable"]
289    #[inline(always)]
290    pub fn micro_tlb2_invalid_en(&self) -> MICRO_TLB_INVALID_EN_R {
291        MICRO_TLB_INVALID_EN_R::new(((self.bits >> 4) & 1) != 0)
292    }
293    #[doc = "Bit 6 - Micro TLB\\[i\\] permission invalid interrupt enable"]
294    #[inline(always)]
295    pub fn micro_tlb3_invalid_en(&self) -> MICRO_TLB_INVALID_EN_R {
296        MICRO_TLB_INVALID_EN_R::new(((self.bits >> 6) & 1) != 0)
297    }
298    #[doc = "Bit 8 - Micro TLB\\[i\\] permission invalid interrupt enable"]
299    #[inline(always)]
300    pub fn micro_tlb4_invalid_en(&self) -> MICRO_TLB_INVALID_EN_R {
301        MICRO_TLB_INVALID_EN_R::new(((self.bits >> 8) & 1) != 0)
302    }
303    #[doc = "Bit 10 - Micro TLB\\[i\\] permission invalid interrupt enable"]
304    #[inline(always)]
305    pub fn micro_tlb5_invalid_en(&self) -> MICRO_TLB_INVALID_EN_R {
306        MICRO_TLB_INVALID_EN_R::new(((self.bits >> 10) & 1) != 0)
307    }
308    #[doc = "Bit 12 - Micro TLB\\[i\\] permission invalid interrupt enable"]
309    #[inline(always)]
310    pub fn micro_tlb6_invalid_en(&self) -> MICRO_TLB_INVALID_EN_R {
311        MICRO_TLB_INVALID_EN_R::new(((self.bits >> 12) & 1) != 0)
312    }
313    #[doc = "Level\\[i\\] page table invalid interrupt enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `l0_page_table_invalid_en` field"]
314    #[inline(always)]
315    pub fn l_page_table_invalid_en(&self, n: u8) -> L_PAGE_TABLE_INVALID_EN_R {
316        #[allow(clippy::no_effect)]
317        [(); 2][n as usize];
318        L_PAGE_TABLE_INVALID_EN_R::new(((self.bits >> (n + 16)) & 1) != 0)
319    }
320    #[doc = "Bit 16 - Level\\[i\\] page table invalid interrupt enable"]
321    #[inline(always)]
322    pub fn l0_page_table_invalid_en(&self) -> L_PAGE_TABLE_INVALID_EN_R {
323        L_PAGE_TABLE_INVALID_EN_R::new(((self.bits >> 16) & 1) != 0)
324    }
325    #[doc = "Bit 17 - Level\\[i\\] page table invalid interrupt enable"]
326    #[inline(always)]
327    pub fn l1_page_table_invalid_en(&self) -> L_PAGE_TABLE_INVALID_EN_R {
328        L_PAGE_TABLE_INVALID_EN_R::new(((self.bits >> 17) & 1) != 0)
329    }
330    #[doc = "Bit 18 - Debug or Prefetch DRAM Invalid Level1 Page Table Enable"]
331    #[inline(always)]
332    pub fn dbg_pf_dram_iv_l1_pt_en(&self) -> DBG_PF_DRAM_IV_L1_PT_EN_R {
333        DBG_PF_DRAM_IV_L1_PT_EN_R::new(((self.bits >> 18) & 1) != 0)
334    }
335    #[doc = "Bit 19 - Debug or Prefetch PTW Cache Invalid Level1 Page Table Enable"]
336    #[inline(always)]
337    pub fn dbg_pf_pc_iv_l1_pt_en(&self) -> DBG_PF_PC_IV_L1_PT_EN_R {
338        DBG_PF_PC_IV_L1_PT_EN_R::new(((self.bits >> 19) & 1) != 0)
339    }
340    #[doc = "Bit 20 - Debug or Prefetch Invalid Page Table Enable"]
341    #[inline(always)]
342    pub fn dbg_pf_l2_iv_pt_en(&self) -> DBG_PF_L2_IV_PT_EN_R {
343        DBG_PF_L2_IV_PT_EN_R::new(((self.bits >> 20) & 1) != 0)
344    }
345}
346impl W {
347    #[doc = "Micro TLB\\[i\\] permission invalid interrupt enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `micro_tlb0_invalid_en` field"]
348    #[inline(always)]
349    #[must_use]
350    pub fn micro_tlb_invalid_en(&mut self, n: u8) -> MICRO_TLB_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
351        #[allow(clippy::no_effect)]
352        [(); 7][n as usize];
353        MICRO_TLB_INVALID_EN_W::new(self, n * 2)
354    }
355    #[doc = "Bit 0 - Micro TLB\\[i\\] permission invalid interrupt enable"]
356    #[inline(always)]
357    #[must_use]
358    pub fn micro_tlb0_invalid_en(&mut self) -> MICRO_TLB_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
359        MICRO_TLB_INVALID_EN_W::new(self, 0)
360    }
361    #[doc = "Bit 2 - Micro TLB\\[i\\] permission invalid interrupt enable"]
362    #[inline(always)]
363    #[must_use]
364    pub fn micro_tlb1_invalid_en(&mut self) -> MICRO_TLB_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
365        MICRO_TLB_INVALID_EN_W::new(self, 2)
366    }
367    #[doc = "Bit 4 - Micro TLB\\[i\\] permission invalid interrupt enable"]
368    #[inline(always)]
369    #[must_use]
370    pub fn micro_tlb2_invalid_en(&mut self) -> MICRO_TLB_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
371        MICRO_TLB_INVALID_EN_W::new(self, 4)
372    }
373    #[doc = "Bit 6 - Micro TLB\\[i\\] permission invalid interrupt enable"]
374    #[inline(always)]
375    #[must_use]
376    pub fn micro_tlb3_invalid_en(&mut self) -> MICRO_TLB_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
377        MICRO_TLB_INVALID_EN_W::new(self, 6)
378    }
379    #[doc = "Bit 8 - Micro TLB\\[i\\] permission invalid interrupt enable"]
380    #[inline(always)]
381    #[must_use]
382    pub fn micro_tlb4_invalid_en(&mut self) -> MICRO_TLB_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
383        MICRO_TLB_INVALID_EN_W::new(self, 8)
384    }
385    #[doc = "Bit 10 - Micro TLB\\[i\\] permission invalid interrupt enable"]
386    #[inline(always)]
387    #[must_use]
388    pub fn micro_tlb5_invalid_en(&mut self) -> MICRO_TLB_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
389        MICRO_TLB_INVALID_EN_W::new(self, 10)
390    }
391    #[doc = "Bit 12 - Micro TLB\\[i\\] permission invalid interrupt enable"]
392    #[inline(always)]
393    #[must_use]
394    pub fn micro_tlb6_invalid_en(&mut self) -> MICRO_TLB_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
395        MICRO_TLB_INVALID_EN_W::new(self, 12)
396    }
397    #[doc = "Level\\[i\\] page table invalid interrupt enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `l0_page_table_invalid_en` field"]
398    #[inline(always)]
399    #[must_use]
400    pub fn l_page_table_invalid_en(
401        &mut self,
402        n: u8,
403    ) -> L_PAGE_TABLE_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
404        #[allow(clippy::no_effect)]
405        [(); 2][n as usize];
406        L_PAGE_TABLE_INVALID_EN_W::new(self, n + 16)
407    }
408    #[doc = "Bit 16 - Level\\[i\\] page table invalid interrupt enable"]
409    #[inline(always)]
410    #[must_use]
411    pub fn l0_page_table_invalid_en(&mut self) -> L_PAGE_TABLE_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
412        L_PAGE_TABLE_INVALID_EN_W::new(self, 16)
413    }
414    #[doc = "Bit 17 - Level\\[i\\] page table invalid interrupt enable"]
415    #[inline(always)]
416    #[must_use]
417    pub fn l1_page_table_invalid_en(&mut self) -> L_PAGE_TABLE_INVALID_EN_W<IOMMU_INT_ENABLE_SPEC> {
418        L_PAGE_TABLE_INVALID_EN_W::new(self, 17)
419    }
420    #[doc = "Bit 18 - Debug or Prefetch DRAM Invalid Level1 Page Table Enable"]
421    #[inline(always)]
422    #[must_use]
423    pub fn dbg_pf_dram_iv_l1_pt_en(&mut self) -> DBG_PF_DRAM_IV_L1_PT_EN_W<IOMMU_INT_ENABLE_SPEC> {
424        DBG_PF_DRAM_IV_L1_PT_EN_W::new(self, 18)
425    }
426    #[doc = "Bit 19 - Debug or Prefetch PTW Cache Invalid Level1 Page Table Enable"]
427    #[inline(always)]
428    #[must_use]
429    pub fn dbg_pf_pc_iv_l1_pt_en(&mut self) -> DBG_PF_PC_IV_L1_PT_EN_W<IOMMU_INT_ENABLE_SPEC> {
430        DBG_PF_PC_IV_L1_PT_EN_W::new(self, 19)
431    }
432    #[doc = "Bit 20 - Debug or Prefetch Invalid Page Table Enable"]
433    #[inline(always)]
434    #[must_use]
435    pub fn dbg_pf_l2_iv_pt_en(&mut self) -> DBG_PF_L2_IV_PT_EN_W<IOMMU_INT_ENABLE_SPEC> {
436        DBG_PF_L2_IV_PT_EN_W::new(self, 20)
437    }
438    #[doc = r" Writes raw bits to the register."]
439    #[doc = r""]
440    #[doc = r" # Safety"]
441    #[doc = r""]
442    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
443    #[inline(always)]
444    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
445        self.bits = bits;
446        self
447    }
448}
449#[doc = "IOMMU Interrupt Enable Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`iommu_int_enable::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`iommu_int_enable::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
450pub struct IOMMU_INT_ENABLE_SPEC;
451impl crate::RegisterSpec for IOMMU_INT_ENABLE_SPEC {
452    type Ux = u32;
453}
454#[doc = "`read()` method returns [`iommu_int_enable::R`](R) reader structure"]
455impl crate::Readable for IOMMU_INT_ENABLE_SPEC {}
456#[doc = "`write(|w| ..)` method takes [`iommu_int_enable::W`](W) writer structure"]
457impl crate::Writable for IOMMU_INT_ENABLE_SPEC {
458    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
459    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
460}
461#[doc = "`reset()` method sets iommu_int_enable to value 0"]
462impl crate::Resettable for IOMMU_INT_ENABLE_SPEC {
463    const RESET_VALUE: Self::Ux = 0;
464}
d1_pac/iommu/iommu_int_enable.rs

d1_pac/iommu/
iommu_int_enable.rs
