d1_pac/i2s_pcm/
i2s_pcm_tx1chsel.rs

1#[doc = "Register `i2s_pcm_tx1chsel` reader"]
2pub type R = crate::R<I2S_PCM_TX1CHSEL_SPEC>;
3#[doc = "Register `i2s_pcm_tx1chsel` writer"]
4pub type W = crate::W<I2S_PCM_TX1CHSEL_SPEC>;
5#[doc = "Field `chen` reader - TX Channel (Slot Enable)\n\nThe bit\\[15:0\\] refer to Slot \\[15:0\\]. When one or more slots are disabled, the affected slots are set to the disable state."]
6pub type CHEN_R = crate::FieldReader<u16>;
7#[doc = "Field `chen` writer - TX Channel (Slot Enable)\n\nThe bit\\[15:0\\] refer to Slot \\[15:0\\]. When one or more slots are disabled, the affected slots are set to the disable state."]
8pub type CHEN_W<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
9#[doc = "Field `chsel` reader - TX Channel (Slot) number select for each output\n\nNum channels = N + 1"]
10pub type CHSEL_R = crate::FieldReader;
11#[doc = "Field `chsel` writer - TX Channel (Slot) number select for each output\n\nNum channels = N + 1"]
12pub type CHSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `offset` reader - TX Offset Tune (TX Data offset to LRCK)\n\n0: No offset\n\nN: Data is offset by N BCLKs to LRCK"]
14pub type OFFSET_R = crate::FieldReader;
15#[doc = "Field `offset` writer - TX Offset Tune (TX Data offset to LRCK)\n\n0: No offset\n\nN: Data is offset by N BCLKs to LRCK"]
16pub type OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
17impl R {
18    #[doc = "Bits 0:15 - TX Channel (Slot Enable)\n\nThe bit\\[15:0\\] refer to Slot \\[15:0\\]. When one or more slots are disabled, the affected slots are set to the disable state."]
19    #[inline(always)]
20    pub fn chen(&self) -> CHEN_R {
21        CHEN_R::new((self.bits & 0xffff) as u16)
22    }
23    #[doc = "Bits 16:19 - TX Channel (Slot) number select for each output\n\nNum channels = N + 1"]
24    #[inline(always)]
25    pub fn chsel(&self) -> CHSEL_R {
26        CHSEL_R::new(((self.bits >> 16) & 0x0f) as u8)
27    }
28    #[doc = "Bits 20:21 - TX Offset Tune (TX Data offset to LRCK)\n\n0: No offset\n\nN: Data is offset by N BCLKs to LRCK"]
29    #[inline(always)]
30    pub fn offset(&self) -> OFFSET_R {
31        OFFSET_R::new(((self.bits >> 20) & 3) as u8)
32    }
33}
34impl W {
35    #[doc = "Bits 0:15 - TX Channel (Slot Enable)\n\nThe bit\\[15:0\\] refer to Slot \\[15:0\\]. When one or more slots are disabled, the affected slots are set to the disable state."]
36    #[inline(always)]
37    #[must_use]
38    pub fn chen(&mut self) -> CHEN_W<I2S_PCM_TX1CHSEL_SPEC> {
39        CHEN_W::new(self, 0)
40    }
41    #[doc = "Bits 16:19 - TX Channel (Slot) number select for each output\n\nNum channels = N + 1"]
42    #[inline(always)]
43    #[must_use]
44    pub fn chsel(&mut self) -> CHSEL_W<I2S_PCM_TX1CHSEL_SPEC> {
45        CHSEL_W::new(self, 16)
46    }
47    #[doc = "Bits 20:21 - TX Offset Tune (TX Data offset to LRCK)\n\n0: No offset\n\nN: Data is offset by N BCLKs to LRCK"]
48    #[inline(always)]
49    #[must_use]
50    pub fn offset(&mut self) -> OFFSET_W<I2S_PCM_TX1CHSEL_SPEC> {
51        OFFSET_W::new(self, 20)
52    }
53    #[doc = r" Writes raw bits to the register."]
54    #[doc = r""]
55    #[doc = r" # Safety"]
56    #[doc = r""]
57    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
58    #[inline(always)]
59    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
60        self.bits = bits;
61        self
62    }
63}
64#[doc = "I2S/PCM TX1 Channel Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_pcm_tx1chsel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_pcm_tx1chsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
65pub struct I2S_PCM_TX1CHSEL_SPEC;
66impl crate::RegisterSpec for I2S_PCM_TX1CHSEL_SPEC {
67    type Ux = u32;
68}
69#[doc = "`read()` method returns [`i2s_pcm_tx1chsel::R`](R) reader structure"]
70impl crate::Readable for I2S_PCM_TX1CHSEL_SPEC {}
71#[doc = "`write(|w| ..)` method takes [`i2s_pcm_tx1chsel::W`](W) writer structure"]
72impl crate::Writable for I2S_PCM_TX1CHSEL_SPEC {
73    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
74    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
75}
76#[doc = "`reset()` method sets i2s_pcm_tx1chsel to value 0"]
77impl crate::Resettable for I2S_PCM_TX1CHSEL_SPEC {
78    const RESET_VALUE: Self::Ux = 0;
79}
d1_pac/i2s_pcm/i2s_pcm_tx1chsel.rs

d1_pac/i2s_pcm/
i2s_pcm_tx1chsel.rs
