d1_pac/i2s_pcm/
i2s_pcm_rxchsel.rs

1#[doc = "Register `i2s_pcm_rxchsel` reader"]
2pub type R = crate::R<I2S_PCM_RXCHSEL_SPEC>;
3#[doc = "Register `i2s_pcm_rxchsel` writer"]
4pub type W = crate::W<I2S_PCM_RXCHSEL_SPEC>;
5#[doc = "Field `chsel` reader - RX Channel (Slot) number select for each output\n\nNum channels = N + 1"]
6pub type CHSEL_R = crate::FieldReader;
7#[doc = "Field `chsel` writer - RX Channel (Slot) number select for each output\n\nNum channels = N + 1"]
8pub type CHSEL_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `offset` reader - RX Offset Tune (RX Data offset to LRCK)\n\n0: No offset\n\nN: Data is offset by N BCLKs to LRCK"]
10pub type OFFSET_R = crate::FieldReader;
11#[doc = "Field `offset` writer - RX Offset Tune (RX Data offset to LRCK)\n\n0: No offset\n\nN: Data is offset by N BCLKs to LRCK"]
12pub type OFFSET_W<'a, REG> = crate::FieldWriter<'a, REG, 2>;
13impl R {
14    #[doc = "Bits 16:19 - RX Channel (Slot) number select for each output\n\nNum channels = N + 1"]
15    #[inline(always)]
16    pub fn chsel(&self) -> CHSEL_R {
17        CHSEL_R::new(((self.bits >> 16) & 0x0f) as u8)
18    }
19    #[doc = "Bits 20:21 - RX Offset Tune (RX Data offset to LRCK)\n\n0: No offset\n\nN: Data is offset by N BCLKs to LRCK"]
20    #[inline(always)]
21    pub fn offset(&self) -> OFFSET_R {
22        OFFSET_R::new(((self.bits >> 20) & 3) as u8)
23    }
24}
25impl W {
26    #[doc = "Bits 16:19 - RX Channel (Slot) number select for each output\n\nNum channels = N + 1"]
27    #[inline(always)]
28    #[must_use]
29    pub fn chsel(&mut self) -> CHSEL_W<I2S_PCM_RXCHSEL_SPEC> {
30        CHSEL_W::new(self, 16)
31    }
32    #[doc = "Bits 20:21 - RX Offset Tune (RX Data offset to LRCK)\n\n0: No offset\n\nN: Data is offset by N BCLKs to LRCK"]
33    #[inline(always)]
34    #[must_use]
35    pub fn offset(&mut self) -> OFFSET_W<I2S_PCM_RXCHSEL_SPEC> {
36        OFFSET_W::new(self, 20)
37    }
38    #[doc = r" Writes raw bits to the register."]
39    #[doc = r""]
40    #[doc = r" # Safety"]
41    #[doc = r""]
42    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
43    #[inline(always)]
44    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
45        self.bits = bits;
46        self
47    }
48}
49#[doc = "I2S/PCM RX Channel Select Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_pcm_rxchsel::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_pcm_rxchsel::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
50pub struct I2S_PCM_RXCHSEL_SPEC;
51impl crate::RegisterSpec for I2S_PCM_RXCHSEL_SPEC {
52    type Ux = u32;
53}
54#[doc = "`read()` method returns [`i2s_pcm_rxchsel::R`](R) reader structure"]
55impl crate::Readable for I2S_PCM_RXCHSEL_SPEC {}
56#[doc = "`write(|w| ..)` method takes [`i2s_pcm_rxchsel::W`](W) writer structure"]
57impl crate::Writable for I2S_PCM_RXCHSEL_SPEC {
58    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
59    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
60}
61#[doc = "`reset()` method sets i2s_pcm_rxchsel to value 0"]
62impl crate::Resettable for I2S_PCM_RXCHSEL_SPEC {
63    const RESET_VALUE: Self::Ux = 0;
64}
d1_pac/i2s_pcm/i2s_pcm_rxchsel.rs

d1_pac/i2s_pcm/
i2s_pcm_rxchsel.rs
