d1_pac/i2s_pcm/
i2s_pcm_fmt0.rs

1#[doc = "Register `i2s_pcm_fmt0` reader"]
2pub type R = crate::R<I2S_PCM_FMT0_SPEC>;
3#[doc = "Register `i2s_pcm_fmt0` writer"]
4pub type W = crate::W<I2S_PCM_FMT0_SPEC>;
5#[doc = "Field `sw` reader - Slot Width Select"]
6pub type SW_R = crate::FieldReader<SW_A>;
7#[doc = "Slot Width Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum SW_A {
11    #[doc = "1: 8-bit"]
12    BITS_8 = 1,
13    #[doc = "2: 12-bit"]
14    BITS_12 = 2,
15    #[doc = "3: 16-bit"]
16    BITS_16 = 3,
17    #[doc = "4: 20-bit"]
18    BITS_20 = 4,
19    #[doc = "5: 24-bit"]
20    BITS_24 = 5,
21    #[doc = "6: 28-bit"]
22    BITS_28 = 6,
23    #[doc = "7: 32-bit"]
24    BITS_32 = 7,
25}
26impl From<SW_A> for u8 {
27    #[inline(always)]
28    fn from(variant: SW_A) -> Self {
29        variant as _
30    }
31}
32impl crate::FieldSpec for SW_A {
33    type Ux = u8;
34}
35impl SW_R {
36    #[doc = "Get enumerated values variant"]
37    #[inline(always)]
38    pub const fn variant(&self) -> SW_A {
39        match self.bits {
40            1 => SW_A::BITS_8,
41            2 => SW_A::BITS_12,
42            3 => SW_A::BITS_16,
43            4 => SW_A::BITS_20,
44            5 => SW_A::BITS_24,
45            6 => SW_A::BITS_28,
46            7 => SW_A::BITS_32,
47            _ => unreachable!(),
48        }
49    }
50    #[doc = "8-bit"]
51    #[inline(always)]
52    pub fn is_bits_8(&self) -> bool {
53        *self == SW_A::BITS_8
54    }
55    #[doc = "12-bit"]
56    #[inline(always)]
57    pub fn is_bits_12(&self) -> bool {
58        *self == SW_A::BITS_12
59    }
60    #[doc = "16-bit"]
61    #[inline(always)]
62    pub fn is_bits_16(&self) -> bool {
63        *self == SW_A::BITS_16
64    }
65    #[doc = "20-bit"]
66    #[inline(always)]
67    pub fn is_bits_20(&self) -> bool {
68        *self == SW_A::BITS_20
69    }
70    #[doc = "24-bit"]
71    #[inline(always)]
72    pub fn is_bits_24(&self) -> bool {
73        *self == SW_A::BITS_24
74    }
75    #[doc = "28-bit"]
76    #[inline(always)]
77    pub fn is_bits_28(&self) -> bool {
78        *self == SW_A::BITS_28
79    }
80    #[doc = "32-bit"]
81    #[inline(always)]
82    pub fn is_bits_32(&self) -> bool {
83        *self == SW_A::BITS_32
84    }
85}
86#[doc = "Field `sw` writer - Slot Width Select"]
87pub type SW_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SW_A>;
88impl<'a, REG> SW_W<'a, REG>
89where
90    REG: crate::Writable + crate::RegisterSpec,
91    REG::Ux: From<u8>,
92{
93    #[doc = "8-bit"]
94    #[inline(always)]
95    pub fn bits_8(self) -> &'a mut crate::W<REG> {
96        self.variant(SW_A::BITS_8)
97    }
98    #[doc = "12-bit"]
99    #[inline(always)]
100    pub fn bits_12(self) -> &'a mut crate::W<REG> {
101        self.variant(SW_A::BITS_12)
102    }
103    #[doc = "16-bit"]
104    #[inline(always)]
105    pub fn bits_16(self) -> &'a mut crate::W<REG> {
106        self.variant(SW_A::BITS_16)
107    }
108    #[doc = "20-bit"]
109    #[inline(always)]
110    pub fn bits_20(self) -> &'a mut crate::W<REG> {
111        self.variant(SW_A::BITS_20)
112    }
113    #[doc = "24-bit"]
114    #[inline(always)]
115    pub fn bits_24(self) -> &'a mut crate::W<REG> {
116        self.variant(SW_A::BITS_24)
117    }
118    #[doc = "28-bit"]
119    #[inline(always)]
120    pub fn bits_28(self) -> &'a mut crate::W<REG> {
121        self.variant(SW_A::BITS_28)
122    }
123    #[doc = "32-bit"]
124    #[inline(always)]
125    pub fn bits_32(self) -> &'a mut crate::W<REG> {
126        self.variant(SW_A::BITS_32)
127    }
128}
129#[doc = "Field `edge_transfer` reader - Edge Transfer"]
130pub type EDGE_TRANSFER_R = crate::BitReader<EDGE_TRANSFER_A>;
131#[doc = "Edge Transfer\n\nValue on reset: 0"]
132#[derive(Clone, Copy, Debug, PartialEq, Eq)]
133pub enum EDGE_TRANSFER_A {
134    #[doc = "0: DOUT drives data and DIN sample data at alternate BCLK edge"]
135    ALTERNATE = 0,
136    #[doc = "1: DOUT drives data and DIN sample data at same BCLK edge"]
137    SAME = 1,
138}
139impl From<EDGE_TRANSFER_A> for bool {
140    #[inline(always)]
141    fn from(variant: EDGE_TRANSFER_A) -> Self {
142        variant as u8 != 0
143    }
144}
145impl EDGE_TRANSFER_R {
146    #[doc = "Get enumerated values variant"]
147    #[inline(always)]
148    pub const fn variant(&self) -> EDGE_TRANSFER_A {
149        match self.bits {
150            false => EDGE_TRANSFER_A::ALTERNATE,
151            true => EDGE_TRANSFER_A::SAME,
152        }
153    }
154    #[doc = "DOUT drives data and DIN sample data at alternate BCLK edge"]
155    #[inline(always)]
156    pub fn is_alternate(&self) -> bool {
157        *self == EDGE_TRANSFER_A::ALTERNATE
158    }
159    #[doc = "DOUT drives data and DIN sample data at same BCLK edge"]
160    #[inline(always)]
161    pub fn is_same(&self) -> bool {
162        *self == EDGE_TRANSFER_A::SAME
163    }
164}
165#[doc = "Field `edge_transfer` writer - Edge Transfer"]
166pub type EDGE_TRANSFER_W<'a, REG> = crate::BitWriter<'a, REG, EDGE_TRANSFER_A>;
167impl<'a, REG> EDGE_TRANSFER_W<'a, REG>
168where
169    REG: crate::Writable + crate::RegisterSpec,
170{
171    #[doc = "DOUT drives data and DIN sample data at alternate BCLK edge"]
172    #[inline(always)]
173    pub fn alternate(self) -> &'a mut crate::W<REG> {
174        self.variant(EDGE_TRANSFER_A::ALTERNATE)
175    }
176    #[doc = "DOUT drives data and DIN sample data at same BCLK edge"]
177    #[inline(always)]
178    pub fn same(self) -> &'a mut crate::W<REG> {
179        self.variant(EDGE_TRANSFER_A::SAME)
180    }
181}
182#[doc = "Field `sr` reader - Sample Resolution"]
183pub type SR_R = crate::FieldReader<SR_A>;
184#[doc = "Sample Resolution\n\nValue on reset: 0"]
185#[derive(Clone, Copy, Debug, PartialEq, Eq)]
186#[repr(u8)]
187pub enum SR_A {
188    #[doc = "1: 8-bit"]
189    BITS_8 = 1,
190    #[doc = "2: 12-bit"]
191    BITS_12 = 2,
192    #[doc = "3: 16-bit"]
193    BITS_16 = 3,
194    #[doc = "4: 20-bit"]
195    BITS_20 = 4,
196    #[doc = "5: 24-bit"]
197    BITS_24 = 5,
198    #[doc = "6: 28-bit"]
199    BITS_28 = 6,
200    #[doc = "7: 32-bit"]
201    BITS_32 = 7,
202}
203impl From<SR_A> for u8 {
204    #[inline(always)]
205    fn from(variant: SR_A) -> Self {
206        variant as _
207    }
208}
209impl crate::FieldSpec for SR_A {
210    type Ux = u8;
211}
212impl SR_R {
213    #[doc = "Get enumerated values variant"]
214    #[inline(always)]
215    pub const fn variant(&self) -> SR_A {
216        match self.bits {
217            1 => SR_A::BITS_8,
218            2 => SR_A::BITS_12,
219            3 => SR_A::BITS_16,
220            4 => SR_A::BITS_20,
221            5 => SR_A::BITS_24,
222            6 => SR_A::BITS_28,
223            7 => SR_A::BITS_32,
224            _ => unreachable!(),
225        }
226    }
227    #[doc = "8-bit"]
228    #[inline(always)]
229    pub fn is_bits_8(&self) -> bool {
230        *self == SR_A::BITS_8
231    }
232    #[doc = "12-bit"]
233    #[inline(always)]
234    pub fn is_bits_12(&self) -> bool {
235        *self == SR_A::BITS_12
236    }
237    #[doc = "16-bit"]
238    #[inline(always)]
239    pub fn is_bits_16(&self) -> bool {
240        *self == SR_A::BITS_16
241    }
242    #[doc = "20-bit"]
243    #[inline(always)]
244    pub fn is_bits_20(&self) -> bool {
245        *self == SR_A::BITS_20
246    }
247    #[doc = "24-bit"]
248    #[inline(always)]
249    pub fn is_bits_24(&self) -> bool {
250        *self == SR_A::BITS_24
251    }
252    #[doc = "28-bit"]
253    #[inline(always)]
254    pub fn is_bits_28(&self) -> bool {
255        *self == SR_A::BITS_28
256    }
257    #[doc = "32-bit"]
258    #[inline(always)]
259    pub fn is_bits_32(&self) -> bool {
260        *self == SR_A::BITS_32
261    }
262}
263#[doc = "Field `sr` writer - Sample Resolution"]
264pub type SR_W<'a, REG> = crate::FieldWriter<'a, REG, 3, SR_A>;
265impl<'a, REG> SR_W<'a, REG>
266where
267    REG: crate::Writable + crate::RegisterSpec,
268    REG::Ux: From<u8>,
269{
270    #[doc = "8-bit"]
271    #[inline(always)]
272    pub fn bits_8(self) -> &'a mut crate::W<REG> {
273        self.variant(SR_A::BITS_8)
274    }
275    #[doc = "12-bit"]
276    #[inline(always)]
277    pub fn bits_12(self) -> &'a mut crate::W<REG> {
278        self.variant(SR_A::BITS_12)
279    }
280    #[doc = "16-bit"]
281    #[inline(always)]
282    pub fn bits_16(self) -> &'a mut crate::W<REG> {
283        self.variant(SR_A::BITS_16)
284    }
285    #[doc = "20-bit"]
286    #[inline(always)]
287    pub fn bits_20(self) -> &'a mut crate::W<REG> {
288        self.variant(SR_A::BITS_20)
289    }
290    #[doc = "24-bit"]
291    #[inline(always)]
292    pub fn bits_24(self) -> &'a mut crate::W<REG> {
293        self.variant(SR_A::BITS_24)
294    }
295    #[doc = "28-bit"]
296    #[inline(always)]
297    pub fn bits_28(self) -> &'a mut crate::W<REG> {
298        self.variant(SR_A::BITS_28)
299    }
300    #[doc = "32-bit"]
301    #[inline(always)]
302    pub fn bits_32(self) -> &'a mut crate::W<REG> {
303        self.variant(SR_A::BITS_32)
304    }
305}
306#[doc = "Field `blck_polarity` reader - BCLK Polarity"]
307pub type BLCK_POLARITY_R = crate::BitReader<BLCK_POLARITY_A>;
308#[doc = "BCLK Polarity\n\nValue on reset: 0"]
309#[derive(Clone, Copy, Debug, PartialEq, Eq)]
310pub enum BLCK_POLARITY_A {
311    #[doc = "0: DOUT drives data at negative edge"]
312    NORMAL = 0,
313    #[doc = "1: DOUT drives data at positive edge"]
314    INVERT = 1,
315}
316impl From<BLCK_POLARITY_A> for bool {
317    #[inline(always)]
318    fn from(variant: BLCK_POLARITY_A) -> Self {
319        variant as u8 != 0
320    }
321}
322impl BLCK_POLARITY_R {
323    #[doc = "Get enumerated values variant"]
324    #[inline(always)]
325    pub const fn variant(&self) -> BLCK_POLARITY_A {
326        match self.bits {
327            false => BLCK_POLARITY_A::NORMAL,
328            true => BLCK_POLARITY_A::INVERT,
329        }
330    }
331    #[doc = "DOUT drives data at negative edge"]
332    #[inline(always)]
333    pub fn is_normal(&self) -> bool {
334        *self == BLCK_POLARITY_A::NORMAL
335    }
336    #[doc = "DOUT drives data at positive edge"]
337    #[inline(always)]
338    pub fn is_invert(&self) -> bool {
339        *self == BLCK_POLARITY_A::INVERT
340    }
341}
342#[doc = "Field `blck_polarity` writer - BCLK Polarity"]
343pub type BLCK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG, BLCK_POLARITY_A>;
344impl<'a, REG> BLCK_POLARITY_W<'a, REG>
345where
346    REG: crate::Writable + crate::RegisterSpec,
347{
348    #[doc = "DOUT drives data at negative edge"]
349    #[inline(always)]
350    pub fn normal(self) -> &'a mut crate::W<REG> {
351        self.variant(BLCK_POLARITY_A::NORMAL)
352    }
353    #[doc = "DOUT drives data at positive edge"]
354    #[inline(always)]
355    pub fn invert(self) -> &'a mut crate::W<REG> {
356        self.variant(BLCK_POLARITY_A::INVERT)
357    }
358}
359#[doc = "Field `lrck_period` reader - Number of BCLKs per channel of the sample frame. This value is interpreted as follows:\n\nPCM mode: Number of BCLKs within (Left + Right) channel width.\n\nI2S/Left-justified/Right-justified: Number of BCLKs within each channel width (Left or Right)\n\nPeriod = N + 1\n\ne.g. N = 7: 8 BCLKs width"]
360pub type LRCK_PERIOD_R = crate::FieldReader<u16>;
361#[doc = "Field `lrck_period` writer - Number of BCLKs per channel of the sample frame. This value is interpreted as follows:\n\nPCM mode: Number of BCLKs within (Left + Right) channel width.\n\nI2S/Left-justified/Right-justified: Number of BCLKs within each channel width (Left or Right)\n\nPeriod = N + 1\n\ne.g. N = 7: 8 BCLKs width"]
362pub type LRCK_PERIOD_W<'a, REG> = crate::FieldWriter<'a, REG, 10, u16>;
363#[doc = "Field `lrck_polarity` reader - LRCK Polarity"]
364pub type LRCK_POLARITY_R = crate::BitReader<LRCK_POLARITY_A>;
365#[doc = "LRCK Polarity\n\nValue on reset: 0"]
366#[derive(Clone, Copy, Debug, PartialEq, Eq)]
367pub enum LRCK_POLARITY_A {
368    #[doc = "0: I2S/Left-justified/Right-justified: Left-channel when LRCK is low\n\nPCM: LRCK asserted at negative edge."]
369    LOW = 0,
370    #[doc = "1: I2S/LeftJustified/Right-justified: Left-channel when LRCK is high\n\nPCM: LRCK asserted at positive edge."]
371    HIGH = 1,
372}
373impl From<LRCK_POLARITY_A> for bool {
374    #[inline(always)]
375    fn from(variant: LRCK_POLARITY_A) -> Self {
376        variant as u8 != 0
377    }
378}
379impl LRCK_POLARITY_R {
380    #[doc = "Get enumerated values variant"]
381    #[inline(always)]
382    pub const fn variant(&self) -> LRCK_POLARITY_A {
383        match self.bits {
384            false => LRCK_POLARITY_A::LOW,
385            true => LRCK_POLARITY_A::HIGH,
386        }
387    }
388    #[doc = "I2S/Left-justified/Right-justified: Left-channel when LRCK is low\n\nPCM: LRCK asserted at negative edge."]
389    #[inline(always)]
390    pub fn is_low(&self) -> bool {
391        *self == LRCK_POLARITY_A::LOW
392    }
393    #[doc = "I2S/LeftJustified/Right-justified: Left-channel when LRCK is high\n\nPCM: LRCK asserted at positive edge."]
394    #[inline(always)]
395    pub fn is_high(&self) -> bool {
396        *self == LRCK_POLARITY_A::HIGH
397    }
398}
399#[doc = "Field `lrck_polarity` writer - LRCK Polarity"]
400pub type LRCK_POLARITY_W<'a, REG> = crate::BitWriter<'a, REG, LRCK_POLARITY_A>;
401impl<'a, REG> LRCK_POLARITY_W<'a, REG>
402where
403    REG: crate::Writable + crate::RegisterSpec,
404{
405    #[doc = "I2S/Left-justified/Right-justified: Left-channel when LRCK is low\n\nPCM: LRCK asserted at negative edge."]
406    #[inline(always)]
407    pub fn low(self) -> &'a mut crate::W<REG> {
408        self.variant(LRCK_POLARITY_A::LOW)
409    }
410    #[doc = "I2S/LeftJustified/Right-justified: Left-channel when LRCK is high\n\nPCM: LRCK asserted at positive edge."]
411    #[inline(always)]
412    pub fn high(self) -> &'a mut crate::W<REG> {
413        self.variant(LRCK_POLARITY_A::HIGH)
414    }
415}
416#[doc = "Field `lrck_width` reader - LRCK Width (only applies to the PCM mode)"]
417pub type LRCK_WIDTH_R = crate::BitReader<LRCK_WIDTH_A>;
418#[doc = "LRCK Width (only applies to the PCM mode)\n\nValue on reset: 0"]
419#[derive(Clone, Copy, Debug, PartialEq, Eq)]
420pub enum LRCK_WIDTH_A {
421    #[doc = "0: LRCK = 1 BCLK Width"]
422    SHORT = 0,
423    #[doc = "1: LRCK = 2 BCLK Width"]
424    LONG = 1,
425}
426impl From<LRCK_WIDTH_A> for bool {
427    #[inline(always)]
428    fn from(variant: LRCK_WIDTH_A) -> Self {
429        variant as u8 != 0
430    }
431}
432impl LRCK_WIDTH_R {
433    #[doc = "Get enumerated values variant"]
434    #[inline(always)]
435    pub const fn variant(&self) -> LRCK_WIDTH_A {
436        match self.bits {
437            false => LRCK_WIDTH_A::SHORT,
438            true => LRCK_WIDTH_A::LONG,
439        }
440    }
441    #[doc = "LRCK = 1 BCLK Width"]
442    #[inline(always)]
443    pub fn is_short(&self) -> bool {
444        *self == LRCK_WIDTH_A::SHORT
445    }
446    #[doc = "LRCK = 2 BCLK Width"]
447    #[inline(always)]
448    pub fn is_long(&self) -> bool {
449        *self == LRCK_WIDTH_A::LONG
450    }
451}
452#[doc = "Field `lrck_width` writer - LRCK Width (only applies to the PCM mode)"]
453pub type LRCK_WIDTH_W<'a, REG> = crate::BitWriter<'a, REG, LRCK_WIDTH_A>;
454impl<'a, REG> LRCK_WIDTH_W<'a, REG>
455where
456    REG: crate::Writable + crate::RegisterSpec,
457{
458    #[doc = "LRCK = 1 BCLK Width"]
459    #[inline(always)]
460    pub fn short(self) -> &'a mut crate::W<REG> {
461        self.variant(LRCK_WIDTH_A::SHORT)
462    }
463    #[doc = "LRCK = 2 BCLK Width"]
464    #[inline(always)]
465    pub fn long(self) -> &'a mut crate::W<REG> {
466        self.variant(LRCK_WIDTH_A::LONG)
467    }
468}
469impl R {
470    #[doc = "Bits 0:2 - Slot Width Select"]
471    #[inline(always)]
472    pub fn sw(&self) -> SW_R {
473        SW_R::new((self.bits & 7) as u8)
474    }
475    #[doc = "Bit 3 - Edge Transfer"]
476    #[inline(always)]
477    pub fn edge_transfer(&self) -> EDGE_TRANSFER_R {
478        EDGE_TRANSFER_R::new(((self.bits >> 3) & 1) != 0)
479    }
480    #[doc = "Bits 4:6 - Sample Resolution"]
481    #[inline(always)]
482    pub fn sr(&self) -> SR_R {
483        SR_R::new(((self.bits >> 4) & 7) as u8)
484    }
485    #[doc = "Bit 7 - BCLK Polarity"]
486    #[inline(always)]
487    pub fn blck_polarity(&self) -> BLCK_POLARITY_R {
488        BLCK_POLARITY_R::new(((self.bits >> 7) & 1) != 0)
489    }
490    #[doc = "Bits 8:17 - Number of BCLKs per channel of the sample frame. This value is interpreted as follows:\n\nPCM mode: Number of BCLKs within (Left + Right) channel width.\n\nI2S/Left-justified/Right-justified: Number of BCLKs within each channel width (Left or Right)\n\nPeriod = N + 1\n\ne.g. N = 7: 8 BCLKs width"]
491    #[inline(always)]
492    pub fn lrck_period(&self) -> LRCK_PERIOD_R {
493        LRCK_PERIOD_R::new(((self.bits >> 8) & 0x03ff) as u16)
494    }
495    #[doc = "Bit 19 - LRCK Polarity"]
496    #[inline(always)]
497    pub fn lrck_polarity(&self) -> LRCK_POLARITY_R {
498        LRCK_POLARITY_R::new(((self.bits >> 19) & 1) != 0)
499    }
500    #[doc = "Bit 30 - LRCK Width (only applies to the PCM mode)"]
501    #[inline(always)]
502    pub fn lrck_width(&self) -> LRCK_WIDTH_R {
503        LRCK_WIDTH_R::new(((self.bits >> 30) & 1) != 0)
504    }
505}
506impl W {
507    #[doc = "Bits 0:2 - Slot Width Select"]
508    #[inline(always)]
509    #[must_use]
510    pub fn sw(&mut self) -> SW_W<I2S_PCM_FMT0_SPEC> {
511        SW_W::new(self, 0)
512    }
513    #[doc = "Bit 3 - Edge Transfer"]
514    #[inline(always)]
515    #[must_use]
516    pub fn edge_transfer(&mut self) -> EDGE_TRANSFER_W<I2S_PCM_FMT0_SPEC> {
517        EDGE_TRANSFER_W::new(self, 3)
518    }
519    #[doc = "Bits 4:6 - Sample Resolution"]
520    #[inline(always)]
521    #[must_use]
522    pub fn sr(&mut self) -> SR_W<I2S_PCM_FMT0_SPEC> {
523        SR_W::new(self, 4)
524    }
525    #[doc = "Bit 7 - BCLK Polarity"]
526    #[inline(always)]
527    #[must_use]
528    pub fn blck_polarity(&mut self) -> BLCK_POLARITY_W<I2S_PCM_FMT0_SPEC> {
529        BLCK_POLARITY_W::new(self, 7)
530    }
531    #[doc = "Bits 8:17 - Number of BCLKs per channel of the sample frame. This value is interpreted as follows:\n\nPCM mode: Number of BCLKs within (Left + Right) channel width.\n\nI2S/Left-justified/Right-justified: Number of BCLKs within each channel width (Left or Right)\n\nPeriod = N + 1\n\ne.g. N = 7: 8 BCLKs width"]
532    #[inline(always)]
533    #[must_use]
534    pub fn lrck_period(&mut self) -> LRCK_PERIOD_W<I2S_PCM_FMT0_SPEC> {
535        LRCK_PERIOD_W::new(self, 8)
536    }
537    #[doc = "Bit 19 - LRCK Polarity"]
538    #[inline(always)]
539    #[must_use]
540    pub fn lrck_polarity(&mut self) -> LRCK_POLARITY_W<I2S_PCM_FMT0_SPEC> {
541        LRCK_POLARITY_W::new(self, 19)
542    }
543    #[doc = "Bit 30 - LRCK Width (only applies to the PCM mode)"]
544    #[inline(always)]
545    #[must_use]
546    pub fn lrck_width(&mut self) -> LRCK_WIDTH_W<I2S_PCM_FMT0_SPEC> {
547        LRCK_WIDTH_W::new(self, 30)
548    }
549    #[doc = r" Writes raw bits to the register."]
550    #[doc = r""]
551    #[doc = r" # Safety"]
552    #[doc = r""]
553    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
554    #[inline(always)]
555    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
556        self.bits = bits;
557        self
558    }
559}
560#[doc = "I2S/PCM Format Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_pcm_fmt0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_pcm_fmt0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
561pub struct I2S_PCM_FMT0_SPEC;
562impl crate::RegisterSpec for I2S_PCM_FMT0_SPEC {
563    type Ux = u32;
564}
565#[doc = "`read()` method returns [`i2s_pcm_fmt0::R`](R) reader structure"]
566impl crate::Readable for I2S_PCM_FMT0_SPEC {}
567#[doc = "`write(|w| ..)` method takes [`i2s_pcm_fmt0::W`](W) writer structure"]
568impl crate::Writable for I2S_PCM_FMT0_SPEC {
569    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
570    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
571}
572#[doc = "`reset()` method sets i2s_pcm_fmt0 to value 0"]
573impl crate::Resettable for I2S_PCM_FMT0_SPEC {
574    const RESET_VALUE: Self::Ux = 0;
575}
d1_pac/i2s_pcm/i2s_pcm_fmt0.rs

d1_pac/i2s_pcm/
i2s_pcm_fmt0.rs
