d1_pac/i2s_pcm/
i2s_pcm_fctl.rs

1#[doc = "Register `i2s_pcm_fctl` reader"]
2pub type R = crate::R<I2S_PCM_FCTL_SPEC>;
3#[doc = "Register `i2s_pcm_fctl` writer"]
4pub type W = crate::W<I2S_PCM_FCTL_SPEC>;
5#[doc = "Field `rxom` reader - RXFIFO Output Mode\n\nExample for 20-bit received audio sample:\n\nMode 0: APB_RDATA\\[31:0\\] = {RXFIFO\\[31:12\\], 12’h0}\n\nMode 1: APB_RDATA\\[31:0\\] = {12{RXFIFO\\[31\\]}, RXFIFO\\[31:12\\]}\n\nMode 2: APB_RDATA \\[31:0\\] = {RXFIFO\\[31:16\\], 16’h0}\n\nMode 3: APB_RDATA\\[31:0\\] = {16{RXFIFO\\[31\\], RXFIFO\\[31:16\\]}"]
6pub type RXOM_R = crate::FieldReader<RXOM_A>;
7#[doc = "RXFIFO Output Mode\n\nExample for 20-bit received audio sample:\n\nMode 0: APB_RDATA\\[31:0\\] = {RXFIFO\\[31:12\\], 12’h0}\n\nMode 1: APB_RDATA\\[31:0\\] = {12{RXFIFO\\[31\\]}, RXFIFO\\[31:12\\]}\n\nMode 2: APB_RDATA \\[31:0\\] = {RXFIFO\\[31:16\\], 16’h0}\n\nMode 3: APB_RDATA\\[31:0\\] = {16{RXFIFO\\[31\\], RXFIFO\\[31:16\\]}\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum RXOM_A {
11    #[doc = "0: Expanding ‘0’ at LSB of RXFIFO register"]
12    MODE0 = 0,
13    #[doc = "1: Expanding received sample sign bit at MSB of RXFIFO register"]
14    MODE1 = 1,
15    #[doc = "2: Truncating received samples at high half-word of RXFIFO register and low half-word of RXFIFO register is filled by ‘0’"]
16    MODE2 = 2,
17    #[doc = "3: Truncating received samples at low half-word of RXFIFO register and high half-word of RXFIFO register is expanded by its sign bit"]
18    MODE3 = 3,
19}
20impl From<RXOM_A> for u8 {
21    #[inline(always)]
22    fn from(variant: RXOM_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for RXOM_A {
27    type Ux = u8;
28}
29impl RXOM_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> RXOM_A {
33        match self.bits {
34            0 => RXOM_A::MODE0,
35            1 => RXOM_A::MODE1,
36            2 => RXOM_A::MODE2,
37            3 => RXOM_A::MODE3,
38            _ => unreachable!(),
39        }
40    }
41    #[doc = "Expanding ‘0’ at LSB of RXFIFO register"]
42    #[inline(always)]
43    pub fn is_mode0(&self) -> bool {
44        *self == RXOM_A::MODE0
45    }
46    #[doc = "Expanding received sample sign bit at MSB of RXFIFO register"]
47    #[inline(always)]
48    pub fn is_mode1(&self) -> bool {
49        *self == RXOM_A::MODE1
50    }
51    #[doc = "Truncating received samples at high half-word of RXFIFO register and low half-word of RXFIFO register is filled by ‘0’"]
52    #[inline(always)]
53    pub fn is_mode2(&self) -> bool {
54        *self == RXOM_A::MODE2
55    }
56    #[doc = "Truncating received samples at low half-word of RXFIFO register and high half-word of RXFIFO register is expanded by its sign bit"]
57    #[inline(always)]
58    pub fn is_mode3(&self) -> bool {
59        *self == RXOM_A::MODE3
60    }
61}
62#[doc = "Field `rxom` writer - RXFIFO Output Mode\n\nExample for 20-bit received audio sample:\n\nMode 0: APB_RDATA\\[31:0\\] = {RXFIFO\\[31:12\\], 12’h0}\n\nMode 1: APB_RDATA\\[31:0\\] = {12{RXFIFO\\[31\\]}, RXFIFO\\[31:12\\]}\n\nMode 2: APB_RDATA \\[31:0\\] = {RXFIFO\\[31:16\\], 16’h0}\n\nMode 3: APB_RDATA\\[31:0\\] = {16{RXFIFO\\[31\\], RXFIFO\\[31:16\\]}"]
63pub type RXOM_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, RXOM_A>;
64impl<'a, REG> RXOM_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "Expanding ‘0’ at LSB of RXFIFO register"]
70    #[inline(always)]
71    pub fn mode0(self) -> &'a mut crate::W<REG> {
72        self.variant(RXOM_A::MODE0)
73    }
74    #[doc = "Expanding received sample sign bit at MSB of RXFIFO register"]
75    #[inline(always)]
76    pub fn mode1(self) -> &'a mut crate::W<REG> {
77        self.variant(RXOM_A::MODE1)
78    }
79    #[doc = "Truncating received samples at high half-word of RXFIFO register and low half-word of RXFIFO register is filled by ‘0’"]
80    #[inline(always)]
81    pub fn mode2(self) -> &'a mut crate::W<REG> {
82        self.variant(RXOM_A::MODE2)
83    }
84    #[doc = "Truncating received samples at low half-word of RXFIFO register and high half-word of RXFIFO register is expanded by its sign bit"]
85    #[inline(always)]
86    pub fn mode3(self) -> &'a mut crate::W<REG> {
87        self.variant(RXOM_A::MODE3)
88    }
89}
90#[doc = "Field `txim` reader - TXFIFO Input Mode\n\nExample for 20-bit transmitted audio sample:\n\nMode 0: TXFIFO\\[31:0\\] = {APB_WDATA\\[31:12\\], 12’h0}\n\nMode 1: TXFIFO\\[31:0\\] = {APB_WDATA\\[19:0\\], 12’h0}"]
91pub type TXIM_R = crate::BitReader<TXIM_A>;
92#[doc = "TXFIFO Input Mode\n\nExample for 20-bit transmitted audio sample:\n\nMode 0: TXFIFO\\[31:0\\] = {APB_WDATA\\[31:12\\], 12’h0}\n\nMode 1: TXFIFO\\[31:0\\] = {APB_WDATA\\[19:0\\], 12’h0}\n\nValue on reset: 0"]
93#[derive(Clone, Copy, Debug, PartialEq, Eq)]
94pub enum TXIM_A {
95    #[doc = "0: Valid data at the MSB of TXFIFO register"]
96    MODE0 = 0,
97    #[doc = "1: Valid data at the LSB of TXFIFO register"]
98    MODE1 = 1,
99}
100impl From<TXIM_A> for bool {
101    #[inline(always)]
102    fn from(variant: TXIM_A) -> Self {
103        variant as u8 != 0
104    }
105}
106impl TXIM_R {
107    #[doc = "Get enumerated values variant"]
108    #[inline(always)]
109    pub const fn variant(&self) -> TXIM_A {
110        match self.bits {
111            false => TXIM_A::MODE0,
112            true => TXIM_A::MODE1,
113        }
114    }
115    #[doc = "Valid data at the MSB of TXFIFO register"]
116    #[inline(always)]
117    pub fn is_mode0(&self) -> bool {
118        *self == TXIM_A::MODE0
119    }
120    #[doc = "Valid data at the LSB of TXFIFO register"]
121    #[inline(always)]
122    pub fn is_mode1(&self) -> bool {
123        *self == TXIM_A::MODE1
124    }
125}
126#[doc = "Field `txim` writer - TXFIFO Input Mode\n\nExample for 20-bit transmitted audio sample:\n\nMode 0: TXFIFO\\[31:0\\] = {APB_WDATA\\[31:12\\], 12’h0}\n\nMode 1: TXFIFO\\[31:0\\] = {APB_WDATA\\[19:0\\], 12’h0}"]
127pub type TXIM_W<'a, REG> = crate::BitWriter<'a, REG, TXIM_A>;
128impl<'a, REG> TXIM_W<'a, REG>
129where
130    REG: crate::Writable + crate::RegisterSpec,
131{
132    #[doc = "Valid data at the MSB of TXFIFO register"]
133    #[inline(always)]
134    pub fn mode0(self) -> &'a mut crate::W<REG> {
135        self.variant(TXIM_A::MODE0)
136    }
137    #[doc = "Valid data at the LSB of TXFIFO register"]
138    #[inline(always)]
139    pub fn mode1(self) -> &'a mut crate::W<REG> {
140        self.variant(TXIM_A::MODE1)
141    }
142}
143#[doc = "Field `rxtl` reader - RXFIFO Empty Trigger Level\n\nInterrupt and DMA request trigger level for RXFIFO normal condition.\n\nTrigger Level = RXTL + 1"]
144pub type RXTL_R = crate::FieldReader;
145#[doc = "Field `rxtl` writer - RXFIFO Empty Trigger Level\n\nInterrupt and DMA request trigger level for RXFIFO normal condition.\n\nTrigger Level = RXTL + 1"]
146pub type RXTL_W<'a, REG> = crate::FieldWriter<'a, REG, 6>;
147#[doc = "Field `txtl` reader - TXFIFO Empty Trigger Level\n\nInterrupt and DMA request trigger level for TXFIFO normal condition.\n\nTrigger Level = TXTL"]
148pub type TXTL_R = crate::FieldReader;
149#[doc = "Field `txtl` writer - TXFIFO Empty Trigger Level\n\nInterrupt and DMA request trigger level for TXFIFO normal condition.\n\nTrigger Level = TXTL"]
150pub type TXTL_W<'a, REG> = crate::FieldWriter<'a, REG, 7>;
151#[doc = "Field `frx` reader - Flush RXFIFO"]
152pub type FRX_R = crate::BitReader<FRX_A>;
153#[doc = "Flush RXFIFO\n\nValue on reset: 0"]
154#[derive(Clone, Copy, Debug, PartialEq, Eq)]
155pub enum FRX_A {
156    #[doc = "0: `0`"]
157    SELF_CLEAR = 0,
158    #[doc = "1: `1`"]
159    FLUSH = 1,
160}
161impl From<FRX_A> for bool {
162    #[inline(always)]
163    fn from(variant: FRX_A) -> Self {
164        variant as u8 != 0
165    }
166}
167impl FRX_R {
168    #[doc = "Get enumerated values variant"]
169    #[inline(always)]
170    pub const fn variant(&self) -> FRX_A {
171        match self.bits {
172            false => FRX_A::SELF_CLEAR,
173            true => FRX_A::FLUSH,
174        }
175    }
176    #[doc = "`0`"]
177    #[inline(always)]
178    pub fn is_self_clear(&self) -> bool {
179        *self == FRX_A::SELF_CLEAR
180    }
181    #[doc = "`1`"]
182    #[inline(always)]
183    pub fn is_flush(&self) -> bool {
184        *self == FRX_A::FLUSH
185    }
186}
187#[doc = "Field `frx` writer - Flush RXFIFO"]
188pub type FRX_W<'a, REG> = crate::BitWriter<'a, REG, FRX_A>;
189impl<'a, REG> FRX_W<'a, REG>
190where
191    REG: crate::Writable + crate::RegisterSpec,
192{
193    #[doc = "`0`"]
194    #[inline(always)]
195    pub fn self_clear(self) -> &'a mut crate::W<REG> {
196        self.variant(FRX_A::SELF_CLEAR)
197    }
198    #[doc = "`1`"]
199    #[inline(always)]
200    pub fn flush(self) -> &'a mut crate::W<REG> {
201        self.variant(FRX_A::FLUSH)
202    }
203}
204#[doc = "Field `ftx` reader - Flush TXFIFO"]
205pub type FTX_R = crate::BitReader<FTX_A>;
206#[doc = "Flush TXFIFO\n\nValue on reset: 0"]
207#[derive(Clone, Copy, Debug, PartialEq, Eq)]
208pub enum FTX_A {
209    #[doc = "0: `0`"]
210    SELF_CLEAR = 0,
211    #[doc = "1: `1`"]
212    FLUSH = 1,
213}
214impl From<FTX_A> for bool {
215    #[inline(always)]
216    fn from(variant: FTX_A) -> Self {
217        variant as u8 != 0
218    }
219}
220impl FTX_R {
221    #[doc = "Get enumerated values variant"]
222    #[inline(always)]
223    pub const fn variant(&self) -> FTX_A {
224        match self.bits {
225            false => FTX_A::SELF_CLEAR,
226            true => FTX_A::FLUSH,
227        }
228    }
229    #[doc = "`0`"]
230    #[inline(always)]
231    pub fn is_self_clear(&self) -> bool {
232        *self == FTX_A::SELF_CLEAR
233    }
234    #[doc = "`1`"]
235    #[inline(always)]
236    pub fn is_flush(&self) -> bool {
237        *self == FTX_A::FLUSH
238    }
239}
240#[doc = "Field `ftx` writer - Flush TXFIFO"]
241pub type FTX_W<'a, REG> = crate::BitWriter<'a, REG, FTX_A>;
242impl<'a, REG> FTX_W<'a, REG>
243where
244    REG: crate::Writable + crate::RegisterSpec,
245{
246    #[doc = "`0`"]
247    #[inline(always)]
248    pub fn self_clear(self) -> &'a mut crate::W<REG> {
249        self.variant(FTX_A::SELF_CLEAR)
250    }
251    #[doc = "`1`"]
252    #[inline(always)]
253    pub fn flush(self) -> &'a mut crate::W<REG> {
254        self.variant(FTX_A::FLUSH)
255    }
256}
257#[doc = "Field `hub_en` reader - Audio Hub Enable"]
258pub type HUB_EN_R = crate::BitReader;
259#[doc = "Field `hub_en` writer - Audio Hub Enable"]
260pub type HUB_EN_W<'a, REG> = crate::BitWriter<'a, REG>;
261impl R {
262    #[doc = "Bits 0:1 - RXFIFO Output Mode\n\nExample for 20-bit received audio sample:\n\nMode 0: APB_RDATA\\[31:0\\] = {RXFIFO\\[31:12\\], 12’h0}\n\nMode 1: APB_RDATA\\[31:0\\] = {12{RXFIFO\\[31\\]}, RXFIFO\\[31:12\\]}\n\nMode 2: APB_RDATA \\[31:0\\] = {RXFIFO\\[31:16\\], 16’h0}\n\nMode 3: APB_RDATA\\[31:0\\] = {16{RXFIFO\\[31\\], RXFIFO\\[31:16\\]}"]
263    #[inline(always)]
264    pub fn rxom(&self) -> RXOM_R {
265        RXOM_R::new((self.bits & 3) as u8)
266    }
267    #[doc = "Bit 2 - TXFIFO Input Mode\n\nExample for 20-bit transmitted audio sample:\n\nMode 0: TXFIFO\\[31:0\\] = {APB_WDATA\\[31:12\\], 12’h0}\n\nMode 1: TXFIFO\\[31:0\\] = {APB_WDATA\\[19:0\\], 12’h0}"]
268    #[inline(always)]
269    pub fn txim(&self) -> TXIM_R {
270        TXIM_R::new(((self.bits >> 2) & 1) != 0)
271    }
272    #[doc = "Bits 4:9 - RXFIFO Empty Trigger Level\n\nInterrupt and DMA request trigger level for RXFIFO normal condition.\n\nTrigger Level = RXTL + 1"]
273    #[inline(always)]
274    pub fn rxtl(&self) -> RXTL_R {
275        RXTL_R::new(((self.bits >> 4) & 0x3f) as u8)
276    }
277    #[doc = "Bits 12:18 - TXFIFO Empty Trigger Level\n\nInterrupt and DMA request trigger level for TXFIFO normal condition.\n\nTrigger Level = TXTL"]
278    #[inline(always)]
279    pub fn txtl(&self) -> TXTL_R {
280        TXTL_R::new(((self.bits >> 12) & 0x7f) as u8)
281    }
282    #[doc = "Bit 24 - Flush RXFIFO"]
283    #[inline(always)]
284    pub fn frx(&self) -> FRX_R {
285        FRX_R::new(((self.bits >> 24) & 1) != 0)
286    }
287    #[doc = "Bit 25 - Flush TXFIFO"]
288    #[inline(always)]
289    pub fn ftx(&self) -> FTX_R {
290        FTX_R::new(((self.bits >> 25) & 1) != 0)
291    }
292    #[doc = "Bit 31 - Audio Hub Enable"]
293    #[inline(always)]
294    pub fn hub_en(&self) -> HUB_EN_R {
295        HUB_EN_R::new(((self.bits >> 31) & 1) != 0)
296    }
297}
298impl W {
299    #[doc = "Bits 0:1 - RXFIFO Output Mode\n\nExample for 20-bit received audio sample:\n\nMode 0: APB_RDATA\\[31:0\\] = {RXFIFO\\[31:12\\], 12’h0}\n\nMode 1: APB_RDATA\\[31:0\\] = {12{RXFIFO\\[31\\]}, RXFIFO\\[31:12\\]}\n\nMode 2: APB_RDATA \\[31:0\\] = {RXFIFO\\[31:16\\], 16’h0}\n\nMode 3: APB_RDATA\\[31:0\\] = {16{RXFIFO\\[31\\], RXFIFO\\[31:16\\]}"]
300    #[inline(always)]
301    #[must_use]
302    pub fn rxom(&mut self) -> RXOM_W<I2S_PCM_FCTL_SPEC> {
303        RXOM_W::new(self, 0)
304    }
305    #[doc = "Bit 2 - TXFIFO Input Mode\n\nExample for 20-bit transmitted audio sample:\n\nMode 0: TXFIFO\\[31:0\\] = {APB_WDATA\\[31:12\\], 12’h0}\n\nMode 1: TXFIFO\\[31:0\\] = {APB_WDATA\\[19:0\\], 12’h0}"]
306    #[inline(always)]
307    #[must_use]
308    pub fn txim(&mut self) -> TXIM_W<I2S_PCM_FCTL_SPEC> {
309        TXIM_W::new(self, 2)
310    }
311    #[doc = "Bits 4:9 - RXFIFO Empty Trigger Level\n\nInterrupt and DMA request trigger level for RXFIFO normal condition.\n\nTrigger Level = RXTL + 1"]
312    #[inline(always)]
313    #[must_use]
314    pub fn rxtl(&mut self) -> RXTL_W<I2S_PCM_FCTL_SPEC> {
315        RXTL_W::new(self, 4)
316    }
317    #[doc = "Bits 12:18 - TXFIFO Empty Trigger Level\n\nInterrupt and DMA request trigger level for TXFIFO normal condition.\n\nTrigger Level = TXTL"]
318    #[inline(always)]
319    #[must_use]
320    pub fn txtl(&mut self) -> TXTL_W<I2S_PCM_FCTL_SPEC> {
321        TXTL_W::new(self, 12)
322    }
323    #[doc = "Bit 24 - Flush RXFIFO"]
324    #[inline(always)]
325    #[must_use]
326    pub fn frx(&mut self) -> FRX_W<I2S_PCM_FCTL_SPEC> {
327        FRX_W::new(self, 24)
328    }
329    #[doc = "Bit 25 - Flush TXFIFO"]
330    #[inline(always)]
331    #[must_use]
332    pub fn ftx(&mut self) -> FTX_W<I2S_PCM_FCTL_SPEC> {
333        FTX_W::new(self, 25)
334    }
335    #[doc = "Bit 31 - Audio Hub Enable"]
336    #[inline(always)]
337    #[must_use]
338    pub fn hub_en(&mut self) -> HUB_EN_W<I2S_PCM_FCTL_SPEC> {
339        HUB_EN_W::new(self, 31)
340    }
341    #[doc = r" Writes raw bits to the register."]
342    #[doc = r""]
343    #[doc = r" # Safety"]
344    #[doc = r""]
345    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
346    #[inline(always)]
347    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
348        self.bits = bits;
349        self
350    }
351}
352#[doc = "I2S/PCM FIFO Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_pcm_fctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_pcm_fctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
353pub struct I2S_PCM_FCTL_SPEC;
354impl crate::RegisterSpec for I2S_PCM_FCTL_SPEC {
355    type Ux = u32;
356}
357#[doc = "`read()` method returns [`i2s_pcm_fctl::R`](R) reader structure"]
358impl crate::Readable for I2S_PCM_FCTL_SPEC {}
359#[doc = "`write(|w| ..)` method takes [`i2s_pcm_fctl::W`](W) writer structure"]
360impl crate::Writable for I2S_PCM_FCTL_SPEC {
361    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
362    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
363}
364#[doc = "`reset()` method sets i2s_pcm_fctl to value 0"]
365impl crate::Resettable for I2S_PCM_FCTL_SPEC {
366    const RESET_VALUE: Self::Ux = 0;
367}
d1_pac/i2s_pcm/i2s_pcm_fctl.rs

d1_pac/i2s_pcm/
i2s_pcm_fctl.rs
