d1_pac/i2s_pcm/
i2s_pcm_ctl.rs

1#[doc = "Register `i2s_pcm_ctl` reader"]
2pub type R = crate::R<I2S_PCM_CTL_SPEC>;
3#[doc = "Register `i2s_pcm_ctl` writer"]
4pub type W = crate::W<I2S_PCM_CTL_SPEC>;
5#[doc = "Field `gen` reader - Global Enable"]
6pub type GEN_R = crate::BitReader<GEN_A>;
7#[doc = "Global Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum GEN_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<GEN_A> for bool {
16    #[inline(always)]
17    fn from(variant: GEN_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl GEN_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> GEN_A {
25        match self.bits {
26            false => GEN_A::DISABLE,
27            true => GEN_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == GEN_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == GEN_A::ENABLE
39    }
40}
41#[doc = "Field `gen` writer - Global Enable"]
42pub type GEN_W<'a, REG> = crate::BitWriter<'a, REG, GEN_A>;
43impl<'a, REG> GEN_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(GEN_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(GEN_A::ENABLE)
56    }
57}
58#[doc = "Field `rxen` reader - Receiver Block Enable"]
59pub type RXEN_R = crate::BitReader<RXEN_A>;
60#[doc = "Receiver Block Enable\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum RXEN_A {
63    #[doc = "0: `0`"]
64    DISABLE = 0,
65    #[doc = "1: `1`"]
66    ENABLE = 1,
67}
68impl From<RXEN_A> for bool {
69    #[inline(always)]
70    fn from(variant: RXEN_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl RXEN_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> RXEN_A {
78        match self.bits {
79            false => RXEN_A::DISABLE,
80            true => RXEN_A::ENABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_disable(&self) -> bool {
86        *self == RXEN_A::DISABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_enable(&self) -> bool {
91        *self == RXEN_A::ENABLE
92    }
93}
94#[doc = "Field `rxen` writer - Receiver Block Enable"]
95pub type RXEN_W<'a, REG> = crate::BitWriter<'a, REG, RXEN_A>;
96impl<'a, REG> RXEN_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn disable(self) -> &'a mut crate::W<REG> {
103        self.variant(RXEN_A::DISABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn enable(self) -> &'a mut crate::W<REG> {
108        self.variant(RXEN_A::ENABLE)
109    }
110}
111#[doc = "Field `txen` reader - Transmitter Block Enable"]
112pub type TXEN_R = crate::BitReader<TXEN_A>;
113#[doc = "Transmitter Block Enable\n\nValue on reset: 0"]
114#[derive(Clone, Copy, Debug, PartialEq, Eq)]
115pub enum TXEN_A {
116    #[doc = "0: `0`"]
117    DISABLE = 0,
118    #[doc = "1: `1`"]
119    ENABLE = 1,
120}
121impl From<TXEN_A> for bool {
122    #[inline(always)]
123    fn from(variant: TXEN_A) -> Self {
124        variant as u8 != 0
125    }
126}
127impl TXEN_R {
128    #[doc = "Get enumerated values variant"]
129    #[inline(always)]
130    pub const fn variant(&self) -> TXEN_A {
131        match self.bits {
132            false => TXEN_A::DISABLE,
133            true => TXEN_A::ENABLE,
134        }
135    }
136    #[doc = "`0`"]
137    #[inline(always)]
138    pub fn is_disable(&self) -> bool {
139        *self == TXEN_A::DISABLE
140    }
141    #[doc = "`1`"]
142    #[inline(always)]
143    pub fn is_enable(&self) -> bool {
144        *self == TXEN_A::ENABLE
145    }
146}
147#[doc = "Field `txen` writer - Transmitter Block Enable"]
148pub type TXEN_W<'a, REG> = crate::BitWriter<'a, REG, TXEN_A>;
149impl<'a, REG> TXEN_W<'a, REG>
150where
151    REG: crate::Writable + crate::RegisterSpec,
152{
153    #[doc = "`0`"]
154    #[inline(always)]
155    pub fn disable(self) -> &'a mut crate::W<REG> {
156        self.variant(TXEN_A::DISABLE)
157    }
158    #[doc = "`1`"]
159    #[inline(always)]
160    pub fn enable(self) -> &'a mut crate::W<REG> {
161        self.variant(TXEN_A::ENABLE)
162    }
163}
164#[doc = "Field `loopback` reader - Loopback Test"]
165pub type LOOPBACK_R = crate::BitReader<LOOPBACK_A>;
166#[doc = "Loopback Test\n\nValue on reset: 0"]
167#[derive(Clone, Copy, Debug, PartialEq, Eq)]
168pub enum LOOPBACK_A {
169    #[doc = "0: `0`"]
170    NORMAL = 0,
171    #[doc = "1: `1`"]
172    TEST = 1,
173}
174impl From<LOOPBACK_A> for bool {
175    #[inline(always)]
176    fn from(variant: LOOPBACK_A) -> Self {
177        variant as u8 != 0
178    }
179}
180impl LOOPBACK_R {
181    #[doc = "Get enumerated values variant"]
182    #[inline(always)]
183    pub const fn variant(&self) -> LOOPBACK_A {
184        match self.bits {
185            false => LOOPBACK_A::NORMAL,
186            true => LOOPBACK_A::TEST,
187        }
188    }
189    #[doc = "`0`"]
190    #[inline(always)]
191    pub fn is_normal(&self) -> bool {
192        *self == LOOPBACK_A::NORMAL
193    }
194    #[doc = "`1`"]
195    #[inline(always)]
196    pub fn is_test(&self) -> bool {
197        *self == LOOPBACK_A::TEST
198    }
199}
200#[doc = "Field `loopback` writer - Loopback Test"]
201pub type LOOPBACK_W<'a, REG> = crate::BitWriter<'a, REG, LOOPBACK_A>;
202impl<'a, REG> LOOPBACK_W<'a, REG>
203where
204    REG: crate::Writable + crate::RegisterSpec,
205{
206    #[doc = "`0`"]
207    #[inline(always)]
208    pub fn normal(self) -> &'a mut crate::W<REG> {
209        self.variant(LOOPBACK_A::NORMAL)
210    }
211    #[doc = "`1`"]
212    #[inline(always)]
213    pub fn test(self) -> &'a mut crate::W<REG> {
214        self.variant(LOOPBACK_A::TEST)
215    }
216}
217#[doc = "Field `mode_sel` reader - Mode Selection"]
218pub type MODE_SEL_R = crate::FieldReader<MODE_SEL_A>;
219#[doc = "Mode Selection\n\nValue on reset: 0"]
220#[derive(Clone, Copy, Debug, PartialEq, Eq)]
221#[repr(u8)]
222pub enum MODE_SEL_A {
223    #[doc = "0: PCM Mode (offset 0: Long Frame, offset 1: Short Frame)"]
224    PCM = 0,
225    #[doc = "1: Left-justified Mode (offset 0: LJ Mode, offset 1: I2S Mode)"]
226    LEFT = 1,
227    #[doc = "2: Right-justified Mode"]
228    RIGHT = 2,
229}
230impl From<MODE_SEL_A> for u8 {
231    #[inline(always)]
232    fn from(variant: MODE_SEL_A) -> Self {
233        variant as _
234    }
235}
236impl crate::FieldSpec for MODE_SEL_A {
237    type Ux = u8;
238}
239impl MODE_SEL_R {
240    #[doc = "Get enumerated values variant"]
241    #[inline(always)]
242    pub const fn variant(&self) -> MODE_SEL_A {
243        match self.bits {
244            0 => MODE_SEL_A::PCM,
245            1 => MODE_SEL_A::LEFT,
246            2 => MODE_SEL_A::RIGHT,
247            _ => unreachable!(),
248        }
249    }
250    #[doc = "PCM Mode (offset 0: Long Frame, offset 1: Short Frame)"]
251    #[inline(always)]
252    pub fn is_pcm(&self) -> bool {
253        *self == MODE_SEL_A::PCM
254    }
255    #[doc = "Left-justified Mode (offset 0: LJ Mode, offset 1: I2S Mode)"]
256    #[inline(always)]
257    pub fn is_left(&self) -> bool {
258        *self == MODE_SEL_A::LEFT
259    }
260    #[doc = "Right-justified Mode"]
261    #[inline(always)]
262    pub fn is_right(&self) -> bool {
263        *self == MODE_SEL_A::RIGHT
264    }
265}
266#[doc = "Field `mode_sel` writer - Mode Selection"]
267pub type MODE_SEL_W<'a, REG> = crate::FieldWriter<'a, REG, 2, MODE_SEL_A>;
268impl<'a, REG> MODE_SEL_W<'a, REG>
269where
270    REG: crate::Writable + crate::RegisterSpec,
271    REG::Ux: From<u8>,
272{
273    #[doc = "PCM Mode (offset 0: Long Frame, offset 1: Short Frame)"]
274    #[inline(always)]
275    pub fn pcm(self) -> &'a mut crate::W<REG> {
276        self.variant(MODE_SEL_A::PCM)
277    }
278    #[doc = "Left-justified Mode (offset 0: LJ Mode, offset 1: I2S Mode)"]
279    #[inline(always)]
280    pub fn left(self) -> &'a mut crate::W<REG> {
281        self.variant(MODE_SEL_A::LEFT)
282    }
283    #[doc = "Right-justified Mode"]
284    #[inline(always)]
285    pub fn right(self) -> &'a mut crate::W<REG> {
286        self.variant(MODE_SEL_A::RIGHT)
287    }
288}
289#[doc = "Field `out_mute` reader - Data Output Mute Enable"]
290pub type OUT_MUTE_R = crate::BitReader<OUT_MUTE_A>;
291#[doc = "Data Output Mute Enable\n\nValue on reset: 0"]
292#[derive(Clone, Copy, Debug, PartialEq, Eq)]
293pub enum OUT_MUTE_A {
294    #[doc = "0: `0`"]
295    NORMAL = 0,
296    #[doc = "1: `1`"]
297    ZERO = 1,
298}
299impl From<OUT_MUTE_A> for bool {
300    #[inline(always)]
301    fn from(variant: OUT_MUTE_A) -> Self {
302        variant as u8 != 0
303    }
304}
305impl OUT_MUTE_R {
306    #[doc = "Get enumerated values variant"]
307    #[inline(always)]
308    pub const fn variant(&self) -> OUT_MUTE_A {
309        match self.bits {
310            false => OUT_MUTE_A::NORMAL,
311            true => OUT_MUTE_A::ZERO,
312        }
313    }
314    #[doc = "`0`"]
315    #[inline(always)]
316    pub fn is_normal(&self) -> bool {
317        *self == OUT_MUTE_A::NORMAL
318    }
319    #[doc = "`1`"]
320    #[inline(always)]
321    pub fn is_zero(&self) -> bool {
322        *self == OUT_MUTE_A::ZERO
323    }
324}
325#[doc = "Field `out_mute` writer - Data Output Mute Enable"]
326pub type OUT_MUTE_W<'a, REG> = crate::BitWriter<'a, REG, OUT_MUTE_A>;
327impl<'a, REG> OUT_MUTE_W<'a, REG>
328where
329    REG: crate::Writable + crate::RegisterSpec,
330{
331    #[doc = "`0`"]
332    #[inline(always)]
333    pub fn normal(self) -> &'a mut crate::W<REG> {
334        self.variant(OUT_MUTE_A::NORMAL)
335    }
336    #[doc = "`1`"]
337    #[inline(always)]
338    pub fn zero(self) -> &'a mut crate::W<REG> {
339        self.variant(OUT_MUTE_A::ZERO)
340    }
341}
342#[doc = "Field `dout_en[0-3]` reader - Data%s Output Enable"]
343pub type DOUT_EN_R = crate::BitReader<DOUT_EN_A>;
344#[doc = "Data%s Output Enable\n\nValue on reset: 0"]
345#[derive(Clone, Copy, Debug, PartialEq, Eq)]
346pub enum DOUT_EN_A {
347    #[doc = "0: Disabled, Hi-Z State"]
348    DISABLE = 0,
349    #[doc = "1: Enabled"]
350    ENABLE = 1,
351}
352impl From<DOUT_EN_A> for bool {
353    #[inline(always)]
354    fn from(variant: DOUT_EN_A) -> Self {
355        variant as u8 != 0
356    }
357}
358impl DOUT_EN_R {
359    #[doc = "Get enumerated values variant"]
360    #[inline(always)]
361    pub const fn variant(&self) -> DOUT_EN_A {
362        match self.bits {
363            false => DOUT_EN_A::DISABLE,
364            true => DOUT_EN_A::ENABLE,
365        }
366    }
367    #[doc = "Disabled, Hi-Z State"]
368    #[inline(always)]
369    pub fn is_disable(&self) -> bool {
370        *self == DOUT_EN_A::DISABLE
371    }
372    #[doc = "Enabled"]
373    #[inline(always)]
374    pub fn is_enable(&self) -> bool {
375        *self == DOUT_EN_A::ENABLE
376    }
377}
378#[doc = "Field `dout_en[0-3]` writer - Data%s Output Enable"]
379pub type DOUT_EN_W<'a, REG> = crate::BitWriter<'a, REG, DOUT_EN_A>;
380impl<'a, REG> DOUT_EN_W<'a, REG>
381where
382    REG: crate::Writable + crate::RegisterSpec,
383{
384    #[doc = "Disabled, Hi-Z State"]
385    #[inline(always)]
386    pub fn disable(self) -> &'a mut crate::W<REG> {
387        self.variant(DOUT_EN_A::DISABLE)
388    }
389    #[doc = "Enabled"]
390    #[inline(always)]
391    pub fn enable(self) -> &'a mut crate::W<REG> {
392        self.variant(DOUT_EN_A::ENABLE)
393    }
394}
395#[doc = "Field `lrck_out` reader - LRCK Direction Select"]
396pub type LRCK_OUT_R = crate::BitReader<LRCK_OUT_A>;
397#[doc = "LRCK Direction Select\n\nValue on reset: 0"]
398#[derive(Clone, Copy, Debug, PartialEq, Eq)]
399pub enum LRCK_OUT_A {
400    #[doc = "0: `0`"]
401    INPUT = 0,
402    #[doc = "1: `1`"]
403    OUTPUT = 1,
404}
405impl From<LRCK_OUT_A> for bool {
406    #[inline(always)]
407    fn from(variant: LRCK_OUT_A) -> Self {
408        variant as u8 != 0
409    }
410}
411impl LRCK_OUT_R {
412    #[doc = "Get enumerated values variant"]
413    #[inline(always)]
414    pub const fn variant(&self) -> LRCK_OUT_A {
415        match self.bits {
416            false => LRCK_OUT_A::INPUT,
417            true => LRCK_OUT_A::OUTPUT,
418        }
419    }
420    #[doc = "`0`"]
421    #[inline(always)]
422    pub fn is_input(&self) -> bool {
423        *self == LRCK_OUT_A::INPUT
424    }
425    #[doc = "`1`"]
426    #[inline(always)]
427    pub fn is_output(&self) -> bool {
428        *self == LRCK_OUT_A::OUTPUT
429    }
430}
431#[doc = "Field `lrck_out` writer - LRCK Direction Select"]
432pub type LRCK_OUT_W<'a, REG> = crate::BitWriter<'a, REG, LRCK_OUT_A>;
433impl<'a, REG> LRCK_OUT_W<'a, REG>
434where
435    REG: crate::Writable + crate::RegisterSpec,
436{
437    #[doc = "`0`"]
438    #[inline(always)]
439    pub fn input(self) -> &'a mut crate::W<REG> {
440        self.variant(LRCK_OUT_A::INPUT)
441    }
442    #[doc = "`1`"]
443    #[inline(always)]
444    pub fn output(self) -> &'a mut crate::W<REG> {
445        self.variant(LRCK_OUT_A::OUTPUT)
446    }
447}
448#[doc = "Field `bclk_out` reader - Bit Clock Direction Select"]
449pub type BCLK_OUT_R = crate::BitReader<BCLK_OUT_A>;
450#[doc = "Bit Clock Direction Select\n\nValue on reset: 0"]
451#[derive(Clone, Copy, Debug, PartialEq, Eq)]
452pub enum BCLK_OUT_A {
453    #[doc = "0: `0`"]
454    INPUT = 0,
455    #[doc = "1: `1`"]
456    OUTPUT = 1,
457}
458impl From<BCLK_OUT_A> for bool {
459    #[inline(always)]
460    fn from(variant: BCLK_OUT_A) -> Self {
461        variant as u8 != 0
462    }
463}
464impl BCLK_OUT_R {
465    #[doc = "Get enumerated values variant"]
466    #[inline(always)]
467    pub const fn variant(&self) -> BCLK_OUT_A {
468        match self.bits {
469            false => BCLK_OUT_A::INPUT,
470            true => BCLK_OUT_A::OUTPUT,
471        }
472    }
473    #[doc = "`0`"]
474    #[inline(always)]
475    pub fn is_input(&self) -> bool {
476        *self == BCLK_OUT_A::INPUT
477    }
478    #[doc = "`1`"]
479    #[inline(always)]
480    pub fn is_output(&self) -> bool {
481        *self == BCLK_OUT_A::OUTPUT
482    }
483}
484#[doc = "Field `bclk_out` writer - Bit Clock Direction Select"]
485pub type BCLK_OUT_W<'a, REG> = crate::BitWriter<'a, REG, BCLK_OUT_A>;
486impl<'a, REG> BCLK_OUT_W<'a, REG>
487where
488    REG: crate::Writable + crate::RegisterSpec,
489{
490    #[doc = "`0`"]
491    #[inline(always)]
492    pub fn input(self) -> &'a mut crate::W<REG> {
493        self.variant(BCLK_OUT_A::INPUT)
494    }
495    #[doc = "`1`"]
496    #[inline(always)]
497    pub fn output(self) -> &'a mut crate::W<REG> {
498        self.variant(BCLK_OUT_A::OUTPUT)
499    }
500}
501#[doc = "Field `rx_sync_en` reader - RX Synchronize Enable"]
502pub type RX_SYNC_EN_R = crate::BitReader<RX_SYNC_EN_A>;
503#[doc = "RX Synchronize Enable\n\nValue on reset: 0"]
504#[derive(Clone, Copy, Debug, PartialEq, Eq)]
505pub enum RX_SYNC_EN_A {
506    #[doc = "0: `0`"]
507    DISABLE = 0,
508    #[doc = "1: `1`"]
509    ENABLE = 1,
510}
511impl From<RX_SYNC_EN_A> for bool {
512    #[inline(always)]
513    fn from(variant: RX_SYNC_EN_A) -> Self {
514        variant as u8 != 0
515    }
516}
517impl RX_SYNC_EN_R {
518    #[doc = "Get enumerated values variant"]
519    #[inline(always)]
520    pub const fn variant(&self) -> RX_SYNC_EN_A {
521        match self.bits {
522            false => RX_SYNC_EN_A::DISABLE,
523            true => RX_SYNC_EN_A::ENABLE,
524        }
525    }
526    #[doc = "`0`"]
527    #[inline(always)]
528    pub fn is_disable(&self) -> bool {
529        *self == RX_SYNC_EN_A::DISABLE
530    }
531    #[doc = "`1`"]
532    #[inline(always)]
533    pub fn is_enable(&self) -> bool {
534        *self == RX_SYNC_EN_A::ENABLE
535    }
536}
537#[doc = "Field `rx_sync_en` writer - RX Synchronize Enable"]
538pub type RX_SYNC_EN_W<'a, REG> = crate::BitWriter<'a, REG, RX_SYNC_EN_A>;
539impl<'a, REG> RX_SYNC_EN_W<'a, REG>
540where
541    REG: crate::Writable + crate::RegisterSpec,
542{
543    #[doc = "`0`"]
544    #[inline(always)]
545    pub fn disable(self) -> &'a mut crate::W<REG> {
546        self.variant(RX_SYNC_EN_A::DISABLE)
547    }
548    #[doc = "`1`"]
549    #[inline(always)]
550    pub fn enable(self) -> &'a mut crate::W<REG> {
551        self.variant(RX_SYNC_EN_A::ENABLE)
552    }
553}
554#[doc = "Field `rx_sync_en_start` reader - RX Synchronize Enable Start"]
555pub type RX_SYNC_EN_START_R = crate::BitReader<RX_SYNC_EN_START_A>;
556#[doc = "RX Synchronize Enable Start\n\nValue on reset: 0"]
557#[derive(Clone, Copy, Debug, PartialEq, Eq)]
558pub enum RX_SYNC_EN_START_A {
559    #[doc = "0: `0`"]
560    DISABLE = 0,
561    #[doc = "1: `1`"]
562    ENABLE = 1,
563}
564impl From<RX_SYNC_EN_START_A> for bool {
565    #[inline(always)]
566    fn from(variant: RX_SYNC_EN_START_A) -> Self {
567        variant as u8 != 0
568    }
569}
570impl RX_SYNC_EN_START_R {
571    #[doc = "Get enumerated values variant"]
572    #[inline(always)]
573    pub const fn variant(&self) -> RX_SYNC_EN_START_A {
574        match self.bits {
575            false => RX_SYNC_EN_START_A::DISABLE,
576            true => RX_SYNC_EN_START_A::ENABLE,
577        }
578    }
579    #[doc = "`0`"]
580    #[inline(always)]
581    pub fn is_disable(&self) -> bool {
582        *self == RX_SYNC_EN_START_A::DISABLE
583    }
584    #[doc = "`1`"]
585    #[inline(always)]
586    pub fn is_enable(&self) -> bool {
587        *self == RX_SYNC_EN_START_A::ENABLE
588    }
589}
590#[doc = "Field `rx_sync_en_start` writer - RX Synchronize Enable Start"]
591pub type RX_SYNC_EN_START_W<'a, REG> = crate::BitWriter<'a, REG, RX_SYNC_EN_START_A>;
592impl<'a, REG> RX_SYNC_EN_START_W<'a, REG>
593where
594    REG: crate::Writable + crate::RegisterSpec,
595{
596    #[doc = "`0`"]
597    #[inline(always)]
598    pub fn disable(self) -> &'a mut crate::W<REG> {
599        self.variant(RX_SYNC_EN_START_A::DISABLE)
600    }
601    #[doc = "`1`"]
602    #[inline(always)]
603    pub fn enable(self) -> &'a mut crate::W<REG> {
604        self.variant(RX_SYNC_EN_START_A::ENABLE)
605    }
606}
607impl R {
608    #[doc = "Bit 0 - Global Enable"]
609    #[inline(always)]
610    pub fn gen(&self) -> GEN_R {
611        GEN_R::new((self.bits & 1) != 0)
612    }
613    #[doc = "Bit 1 - Receiver Block Enable"]
614    #[inline(always)]
615    pub fn rxen(&self) -> RXEN_R {
616        RXEN_R::new(((self.bits >> 1) & 1) != 0)
617    }
618    #[doc = "Bit 2 - Transmitter Block Enable"]
619    #[inline(always)]
620    pub fn txen(&self) -> TXEN_R {
621        TXEN_R::new(((self.bits >> 2) & 1) != 0)
622    }
623    #[doc = "Bit 3 - Loopback Test"]
624    #[inline(always)]
625    pub fn loopback(&self) -> LOOPBACK_R {
626        LOOPBACK_R::new(((self.bits >> 3) & 1) != 0)
627    }
628    #[doc = "Bits 4:5 - Mode Selection"]
629    #[inline(always)]
630    pub fn mode_sel(&self) -> MODE_SEL_R {
631        MODE_SEL_R::new(((self.bits >> 4) & 3) as u8)
632    }
633    #[doc = "Bit 6 - Data Output Mute Enable"]
634    #[inline(always)]
635    pub fn out_mute(&self) -> OUT_MUTE_R {
636        OUT_MUTE_R::new(((self.bits >> 6) & 1) != 0)
637    }
638    #[doc = "Data[0-3] Output Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dout0_en` field"]
639    #[inline(always)]
640    pub fn dout_en(&self, n: u8) -> DOUT_EN_R {
641        #[allow(clippy::no_effect)]
642        [(); 4][n as usize];
643        DOUT_EN_R::new(((self.bits >> (n + 8)) & 1) != 0)
644    }
645    #[doc = "Bit 8 - Data0 Output Enable"]
646    #[inline(always)]
647    pub fn dout0_en(&self) -> DOUT_EN_R {
648        DOUT_EN_R::new(((self.bits >> 8) & 1) != 0)
649    }
650    #[doc = "Bit 9 - Data1 Output Enable"]
651    #[inline(always)]
652    pub fn dout1_en(&self) -> DOUT_EN_R {
653        DOUT_EN_R::new(((self.bits >> 9) & 1) != 0)
654    }
655    #[doc = "Bit 10 - Data2 Output Enable"]
656    #[inline(always)]
657    pub fn dout2_en(&self) -> DOUT_EN_R {
658        DOUT_EN_R::new(((self.bits >> 10) & 1) != 0)
659    }
660    #[doc = "Bit 11 - Data3 Output Enable"]
661    #[inline(always)]
662    pub fn dout3_en(&self) -> DOUT_EN_R {
663        DOUT_EN_R::new(((self.bits >> 11) & 1) != 0)
664    }
665    #[doc = "Bit 17 - LRCK Direction Select"]
666    #[inline(always)]
667    pub fn lrck_out(&self) -> LRCK_OUT_R {
668        LRCK_OUT_R::new(((self.bits >> 17) & 1) != 0)
669    }
670    #[doc = "Bit 18 - Bit Clock Direction Select"]
671    #[inline(always)]
672    pub fn bclk_out(&self) -> BCLK_OUT_R {
673        BCLK_OUT_R::new(((self.bits >> 18) & 1) != 0)
674    }
675    #[doc = "Bit 20 - RX Synchronize Enable"]
676    #[inline(always)]
677    pub fn rx_sync_en(&self) -> RX_SYNC_EN_R {
678        RX_SYNC_EN_R::new(((self.bits >> 20) & 1) != 0)
679    }
680    #[doc = "Bit 21 - RX Synchronize Enable Start"]
681    #[inline(always)]
682    pub fn rx_sync_en_start(&self) -> RX_SYNC_EN_START_R {
683        RX_SYNC_EN_START_R::new(((self.bits >> 21) & 1) != 0)
684    }
685}
686impl W {
687    #[doc = "Bit 0 - Global Enable"]
688    #[inline(always)]
689    #[must_use]
690    pub fn gen(&mut self) -> GEN_W<I2S_PCM_CTL_SPEC> {
691        GEN_W::new(self, 0)
692    }
693    #[doc = "Bit 1 - Receiver Block Enable"]
694    #[inline(always)]
695    #[must_use]
696    pub fn rxen(&mut self) -> RXEN_W<I2S_PCM_CTL_SPEC> {
697        RXEN_W::new(self, 1)
698    }
699    #[doc = "Bit 2 - Transmitter Block Enable"]
700    #[inline(always)]
701    #[must_use]
702    pub fn txen(&mut self) -> TXEN_W<I2S_PCM_CTL_SPEC> {
703        TXEN_W::new(self, 2)
704    }
705    #[doc = "Bit 3 - Loopback Test"]
706    #[inline(always)]
707    #[must_use]
708    pub fn loopback(&mut self) -> LOOPBACK_W<I2S_PCM_CTL_SPEC> {
709        LOOPBACK_W::new(self, 3)
710    }
711    #[doc = "Bits 4:5 - Mode Selection"]
712    #[inline(always)]
713    #[must_use]
714    pub fn mode_sel(&mut self) -> MODE_SEL_W<I2S_PCM_CTL_SPEC> {
715        MODE_SEL_W::new(self, 4)
716    }
717    #[doc = "Bit 6 - Data Output Mute Enable"]
718    #[inline(always)]
719    #[must_use]
720    pub fn out_mute(&mut self) -> OUT_MUTE_W<I2S_PCM_CTL_SPEC> {
721        OUT_MUTE_W::new(self, 6)
722    }
723    #[doc = "Data[0-3] Output Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `dout0_en` field"]
724    #[inline(always)]
725    #[must_use]
726    pub fn dout_en(&mut self, n: u8) -> DOUT_EN_W<I2S_PCM_CTL_SPEC> {
727        #[allow(clippy::no_effect)]
728        [(); 4][n as usize];
729        DOUT_EN_W::new(self, n + 8)
730    }
731    #[doc = "Bit 8 - Data0 Output Enable"]
732    #[inline(always)]
733    #[must_use]
734    pub fn dout0_en(&mut self) -> DOUT_EN_W<I2S_PCM_CTL_SPEC> {
735        DOUT_EN_W::new(self, 8)
736    }
737    #[doc = "Bit 9 - Data1 Output Enable"]
738    #[inline(always)]
739    #[must_use]
740    pub fn dout1_en(&mut self) -> DOUT_EN_W<I2S_PCM_CTL_SPEC> {
741        DOUT_EN_W::new(self, 9)
742    }
743    #[doc = "Bit 10 - Data2 Output Enable"]
744    #[inline(always)]
745    #[must_use]
746    pub fn dout2_en(&mut self) -> DOUT_EN_W<I2S_PCM_CTL_SPEC> {
747        DOUT_EN_W::new(self, 10)
748    }
749    #[doc = "Bit 11 - Data3 Output Enable"]
750    #[inline(always)]
751    #[must_use]
752    pub fn dout3_en(&mut self) -> DOUT_EN_W<I2S_PCM_CTL_SPEC> {
753        DOUT_EN_W::new(self, 11)
754    }
755    #[doc = "Bit 17 - LRCK Direction Select"]
756    #[inline(always)]
757    #[must_use]
758    pub fn lrck_out(&mut self) -> LRCK_OUT_W<I2S_PCM_CTL_SPEC> {
759        LRCK_OUT_W::new(self, 17)
760    }
761    #[doc = "Bit 18 - Bit Clock Direction Select"]
762    #[inline(always)]
763    #[must_use]
764    pub fn bclk_out(&mut self) -> BCLK_OUT_W<I2S_PCM_CTL_SPEC> {
765        BCLK_OUT_W::new(self, 18)
766    }
767    #[doc = "Bit 20 - RX Synchronize Enable"]
768    #[inline(always)]
769    #[must_use]
770    pub fn rx_sync_en(&mut self) -> RX_SYNC_EN_W<I2S_PCM_CTL_SPEC> {
771        RX_SYNC_EN_W::new(self, 20)
772    }
773    #[doc = "Bit 21 - RX Synchronize Enable Start"]
774    #[inline(always)]
775    #[must_use]
776    pub fn rx_sync_en_start(&mut self) -> RX_SYNC_EN_START_W<I2S_PCM_CTL_SPEC> {
777        RX_SYNC_EN_START_W::new(self, 21)
778    }
779    #[doc = r" Writes raw bits to the register."]
780    #[doc = r""]
781    #[doc = r" # Safety"]
782    #[doc = r""]
783    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
784    #[inline(always)]
785    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
786        self.bits = bits;
787        self
788    }
789}
790#[doc = "I2S/PCM Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_pcm_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_pcm_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
791pub struct I2S_PCM_CTL_SPEC;
792impl crate::RegisterSpec for I2S_PCM_CTL_SPEC {
793    type Ux = u32;
794}
795#[doc = "`read()` method returns [`i2s_pcm_ctl::R`](R) reader structure"]
796impl crate::Readable for I2S_PCM_CTL_SPEC {}
797#[doc = "`write(|w| ..)` method takes [`i2s_pcm_ctl::W`](W) writer structure"]
798impl crate::Writable for I2S_PCM_CTL_SPEC {
799    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
800    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
801}
802#[doc = "`reset()` method sets i2s_pcm_ctl to value 0"]
803impl crate::Resettable for I2S_PCM_CTL_SPEC {
804    const RESET_VALUE: Self::Ux = 0;
805}
d1_pac/i2s_pcm/i2s_pcm_ctl.rs

d1_pac/i2s_pcm/
i2s_pcm_ctl.rs
