d1_pac/i2s_pcm/
i2s_pcm_chcfg.rs

1#[doc = "Register `i2s_pcm_chcfg` reader"]
2pub type R = crate::R<I2S_PCM_CHCFG_SPEC>;
3#[doc = "Register `i2s_pcm_chcfg` writer"]
4pub type W = crate::W<I2S_PCM_CHCFG_SPEC>;
5#[doc = "Field `tx_slot_num` reader - TX Channel/Slot number between CPU/DMA and RXFIFO\n\nChannel or slot = N + 1"]
6pub type TX_SLOT_NUM_R = crate::FieldReader;
7#[doc = "Field `tx_slot_num` writer - TX Channel/Slot number between CPU/DMA and RXFIFO\n\nChannel or slot = N + 1"]
8pub type TX_SLOT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
9#[doc = "Field `rx_slot_num` reader - RX Channel/Slot number between CPU/DMA and RXFIFO\n\nChannel or slot = N + 1"]
10pub type RX_SLOT_NUM_R = crate::FieldReader;
11#[doc = "Field `rx_slot_num` writer - RX Channel/Slot number between CPU/DMA and RXFIFO\n\nChannel or slot = N + 1"]
12pub type RX_SLOT_NUM_W<'a, REG> = crate::FieldWriter<'a, REG, 4>;
13#[doc = "Field `tx_state` reader - "]
14pub type TX_STATE_R = crate::BitReader<TX_STATE_A>;
15#[doc = "\n\nValue on reset: 0"]
16#[derive(Clone, Copy, Debug, PartialEq, Eq)]
17pub enum TX_STATE_A {
18    #[doc = "0: Transfer level 0 in non-transferring slot"]
19    ZERO = 0,
20    #[doc = "1: Turn to Hi-Z State (TDM) in non-transferring slot"]
21    HIZ = 1,
22}
23impl From<TX_STATE_A> for bool {
24    #[inline(always)]
25    fn from(variant: TX_STATE_A) -> Self {
26        variant as u8 != 0
27    }
28}
29impl TX_STATE_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> TX_STATE_A {
33        match self.bits {
34            false => TX_STATE_A::ZERO,
35            true => TX_STATE_A::HIZ,
36        }
37    }
38    #[doc = "Transfer level 0 in non-transferring slot"]
39    #[inline(always)]
40    pub fn is_zero(&self) -> bool {
41        *self == TX_STATE_A::ZERO
42    }
43    #[doc = "Turn to Hi-Z State (TDM) in non-transferring slot"]
44    #[inline(always)]
45    pub fn is_hiz(&self) -> bool {
46        *self == TX_STATE_A::HIZ
47    }
48}
49#[doc = "Field `tx_state` writer - "]
50pub type TX_STATE_W<'a, REG> = crate::BitWriter<'a, REG, TX_STATE_A>;
51impl<'a, REG> TX_STATE_W<'a, REG>
52where
53    REG: crate::Writable + crate::RegisterSpec,
54{
55    #[doc = "Transfer level 0 in non-transferring slot"]
56    #[inline(always)]
57    pub fn zero(self) -> &'a mut crate::W<REG> {
58        self.variant(TX_STATE_A::ZERO)
59    }
60    #[doc = "Turn to Hi-Z State (TDM) in non-transferring slot"]
61    #[inline(always)]
62    pub fn hiz(self) -> &'a mut crate::W<REG> {
63        self.variant(TX_STATE_A::HIZ)
64    }
65}
66#[doc = "Field `tx_slot_hiz` reader - "]
67pub type TX_SLOT_HIZ_R = crate::BitReader<TX_SLOT_HIZ_A>;
68#[doc = "\n\nValue on reset: 0"]
69#[derive(Clone, Copy, Debug, PartialEq, Eq)]
70pub enum TX_SLOT_HIZ_A {
71    #[doc = "0: Normal mode for the last half-cycle of BCLK in the slot"]
72    NORMAL = 0,
73    #[doc = "1: Turn to Hi-Z state for the last half-cycle of BCLK in the slot"]
74    HIZ = 1,
75}
76impl From<TX_SLOT_HIZ_A> for bool {
77    #[inline(always)]
78    fn from(variant: TX_SLOT_HIZ_A) -> Self {
79        variant as u8 != 0
80    }
81}
82impl TX_SLOT_HIZ_R {
83    #[doc = "Get enumerated values variant"]
84    #[inline(always)]
85    pub const fn variant(&self) -> TX_SLOT_HIZ_A {
86        match self.bits {
87            false => TX_SLOT_HIZ_A::NORMAL,
88            true => TX_SLOT_HIZ_A::HIZ,
89        }
90    }
91    #[doc = "Normal mode for the last half-cycle of BCLK in the slot"]
92    #[inline(always)]
93    pub fn is_normal(&self) -> bool {
94        *self == TX_SLOT_HIZ_A::NORMAL
95    }
96    #[doc = "Turn to Hi-Z state for the last half-cycle of BCLK in the slot"]
97    #[inline(always)]
98    pub fn is_hiz(&self) -> bool {
99        *self == TX_SLOT_HIZ_A::HIZ
100    }
101}
102#[doc = "Field `tx_slot_hiz` writer - "]
103pub type TX_SLOT_HIZ_W<'a, REG> = crate::BitWriter<'a, REG, TX_SLOT_HIZ_A>;
104impl<'a, REG> TX_SLOT_HIZ_W<'a, REG>
105where
106    REG: crate::Writable + crate::RegisterSpec,
107{
108    #[doc = "Normal mode for the last half-cycle of BCLK in the slot"]
109    #[inline(always)]
110    pub fn normal(self) -> &'a mut crate::W<REG> {
111        self.variant(TX_SLOT_HIZ_A::NORMAL)
112    }
113    #[doc = "Turn to Hi-Z state for the last half-cycle of BCLK in the slot"]
114    #[inline(always)]
115    pub fn hiz(self) -> &'a mut crate::W<REG> {
116        self.variant(TX_SLOT_HIZ_A::HIZ)
117    }
118}
119impl R {
120    #[doc = "Bits 0:3 - TX Channel/Slot number between CPU/DMA and RXFIFO\n\nChannel or slot = N + 1"]
121    #[inline(always)]
122    pub fn tx_slot_num(&self) -> TX_SLOT_NUM_R {
123        TX_SLOT_NUM_R::new((self.bits & 0x0f) as u8)
124    }
125    #[doc = "Bits 4:7 - RX Channel/Slot number between CPU/DMA and RXFIFO\n\nChannel or slot = N + 1"]
126    #[inline(always)]
127    pub fn rx_slot_num(&self) -> RX_SLOT_NUM_R {
128        RX_SLOT_NUM_R::new(((self.bits >> 4) & 0x0f) as u8)
129    }
130    #[doc = "Bit 8"]
131    #[inline(always)]
132    pub fn tx_state(&self) -> TX_STATE_R {
133        TX_STATE_R::new(((self.bits >> 8) & 1) != 0)
134    }
135    #[doc = "Bit 9"]
136    #[inline(always)]
137    pub fn tx_slot_hiz(&self) -> TX_SLOT_HIZ_R {
138        TX_SLOT_HIZ_R::new(((self.bits >> 9) & 1) != 0)
139    }
140}
141impl W {
142    #[doc = "Bits 0:3 - TX Channel/Slot number between CPU/DMA and RXFIFO\n\nChannel or slot = N + 1"]
143    #[inline(always)]
144    #[must_use]
145    pub fn tx_slot_num(&mut self) -> TX_SLOT_NUM_W<I2S_PCM_CHCFG_SPEC> {
146        TX_SLOT_NUM_W::new(self, 0)
147    }
148    #[doc = "Bits 4:7 - RX Channel/Slot number between CPU/DMA and RXFIFO\n\nChannel or slot = N + 1"]
149    #[inline(always)]
150    #[must_use]
151    pub fn rx_slot_num(&mut self) -> RX_SLOT_NUM_W<I2S_PCM_CHCFG_SPEC> {
152        RX_SLOT_NUM_W::new(self, 4)
153    }
154    #[doc = "Bit 8"]
155    #[inline(always)]
156    #[must_use]
157    pub fn tx_state(&mut self) -> TX_STATE_W<I2S_PCM_CHCFG_SPEC> {
158        TX_STATE_W::new(self, 8)
159    }
160    #[doc = "Bit 9"]
161    #[inline(always)]
162    #[must_use]
163    pub fn tx_slot_hiz(&mut self) -> TX_SLOT_HIZ_W<I2S_PCM_CHCFG_SPEC> {
164        TX_SLOT_HIZ_W::new(self, 9)
165    }
166    #[doc = r" Writes raw bits to the register."]
167    #[doc = r""]
168    #[doc = r" # Safety"]
169    #[doc = r""]
170    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
171    #[inline(always)]
172    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
173        self.bits = bits;
174        self
175    }
176}
177#[doc = "I2S/PCM Channel Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`i2s_pcm_chcfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`i2s_pcm_chcfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
178pub struct I2S_PCM_CHCFG_SPEC;
179impl crate::RegisterSpec for I2S_PCM_CHCFG_SPEC {
180    type Ux = u32;
181}
182#[doc = "`read()` method returns [`i2s_pcm_chcfg::R`](R) reader structure"]
183impl crate::Readable for I2S_PCM_CHCFG_SPEC {}
184#[doc = "`write(|w| ..)` method takes [`i2s_pcm_chcfg::W`](W) writer structure"]
185impl crate::Writable for I2S_PCM_CHCFG_SPEC {
186    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
187    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
188}
189#[doc = "`reset()` method sets i2s_pcm_chcfg to value 0"]
190impl crate::Resettable for I2S_PCM_CHCFG_SPEC {
191    const RESET_VALUE: Self::Ux = 0;
192}
d1_pac/i2s_pcm/i2s_pcm_chcfg.rs

d1_pac/i2s_pcm/
i2s_pcm_chcfg.rs
