d1_pac/i2s_pcm/
fsout_cfg.rs

1#[doc = "Register `fsout_cfg` reader"]
2pub type R = crate::R<FSOUT_CFG_SPEC>;
3#[doc = "Register `fsout_cfg` writer"]
4pub type W = crate::W<FSOUT_CFG_SPEC>;
5#[doc = "Field `fsout_gate` reader - fsout Clock Gate Enable Control"]
6pub type FSOUT_GATE_R = crate::BitReader<FSOUT_GATE_A>;
7#[doc = "fsout Clock Gate Enable Control\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum FSOUT_GATE_A {
10    #[doc = "0: Disable"]
11    DISABLE = 0,
12    #[doc = "1: Enable"]
13    ENABLE = 1,
14}
15impl From<FSOUT_GATE_A> for bool {
16    #[inline(always)]
17    fn from(variant: FSOUT_GATE_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl FSOUT_GATE_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> FSOUT_GATE_A {
25        match self.bits {
26            false => FSOUT_GATE_A::DISABLE,
27            true => FSOUT_GATE_A::ENABLE,
28        }
29    }
30    #[doc = "Disable"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == FSOUT_GATE_A::DISABLE
34    }
35    #[doc = "Enable"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == FSOUT_GATE_A::ENABLE
39    }
40}
41#[doc = "Field `fsout_gate` writer - fsout Clock Gate Enable Control"]
42pub type FSOUT_GATE_W<'a, REG> = crate::BitWriter<'a, REG, FSOUT_GATE_A>;
43impl<'a, REG> FSOUT_GATE_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "Disable"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(FSOUT_GATE_A::DISABLE)
51    }
52    #[doc = "Enable"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(FSOUT_GATE_A::ENABLE)
56    }
57}
58impl R {
59    #[doc = "Bit 20 - fsout Clock Gate Enable Control"]
60    #[inline(always)]
61    pub fn fsout_gate(&self) -> FSOUT_GATE_R {
62        FSOUT_GATE_R::new(((self.bits >> 20) & 1) != 0)
63    }
64}
65impl W {
66    #[doc = "Bit 20 - fsout Clock Gate Enable Control"]
67    #[inline(always)]
68    #[must_use]
69    pub fn fsout_gate(&mut self) -> FSOUT_GATE_W<FSOUT_CFG_SPEC> {
70        FSOUT_GATE_W::new(self, 20)
71    }
72    #[doc = r" Writes raw bits to the register."]
73    #[doc = r""]
74    #[doc = r" # Safety"]
75    #[doc = r""]
76    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
77    #[inline(always)]
78    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
79        self.bits = bits;
80        self
81    }
82}
83#[doc = "ASRC Out Sample Rate Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fsout_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fsout_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
84pub struct FSOUT_CFG_SPEC;
85impl crate::RegisterSpec for FSOUT_CFG_SPEC {
86    type Ux = u32;
87}
88#[doc = "`read()` method returns [`fsout_cfg::R`](R) reader structure"]
89impl crate::Readable for FSOUT_CFG_SPEC {}
90#[doc = "`write(|w| ..)` method takes [`fsout_cfg::W`](W) writer structure"]
91impl crate::Writable for FSOUT_CFG_SPEC {
92    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
93    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
94}
95#[doc = "`reset()` method sets fsout_cfg to value 0"]
96impl crate::Resettable for FSOUT_CFG_SPEC {
97    const RESET_VALUE: Self::Ux = 0;
98}
d1_pac/i2s_pcm/fsout_cfg.rs

d1_pac/i2s_pcm/
fsout_cfg.rs
