d1_pac/gpio/
pio_pow_ms_ctl.rs

1#[doc = "Register `pio_pow_ms_ctl` reader"]
2pub type R = crate::R<PIO_POW_MS_CTL_SPEC>;
3#[doc = "Register `pio_pow_ms_ctl` writer"]
4pub type W = crate::W<PIO_POW_MS_CTL_SPEC>;
5#[doc = "Field `vcc_p_ws_vol_mod_sel[C,D,E,F,G]` reader - VCC_PX Withstand Voltage Mode Select Control"]
6pub type VCC_P_WS_VOL_MOD_SEL_R = crate::BitReader<VCC_P_WS_VOL_MOD_SEL_A>;
7#[doc = "VCC_PX Withstand Voltage Mode Select Control\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum VCC_P_WS_VOL_MOD_SEL_A {
10    #[doc = "0: `0`"]
11    ENABLE = 0,
12    #[doc = "1: `1`"]
13    DISABLE = 1,
14}
15impl From<VCC_P_WS_VOL_MOD_SEL_A> for bool {
16    #[inline(always)]
17    fn from(variant: VCC_P_WS_VOL_MOD_SEL_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl VCC_P_WS_VOL_MOD_SEL_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> VCC_P_WS_VOL_MOD_SEL_A {
25        match self.bits {
26            false => VCC_P_WS_VOL_MOD_SEL_A::ENABLE,
27            true => VCC_P_WS_VOL_MOD_SEL_A::DISABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_enable(&self) -> bool {
33        *self == VCC_P_WS_VOL_MOD_SEL_A::ENABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_disable(&self) -> bool {
38        *self == VCC_P_WS_VOL_MOD_SEL_A::DISABLE
39    }
40}
41#[doc = "Field `vcc_p_ws_vol_mod_sel[C,D,E,F,G]` writer - VCC_PX Withstand Voltage Mode Select Control"]
42pub type VCC_P_WS_VOL_MOD_SEL_W<'a, REG> = crate::BitWriter<'a, REG, VCC_P_WS_VOL_MOD_SEL_A>;
43impl<'a, REG> VCC_P_WS_VOL_MOD_SEL_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn enable(self) -> &'a mut crate::W<REG> {
50        self.variant(VCC_P_WS_VOL_MOD_SEL_A::ENABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn disable(self) -> &'a mut crate::W<REG> {
55        self.variant(VCC_P_WS_VOL_MOD_SEL_A::DISABLE)
56    }
57}
58#[doc = "Field `vccio_ws_vol_mod_sel` reader - VCC_IO Withstand Voltage Mode Select Control"]
59pub type VCCIO_WS_VOL_MOD_SEL_R = crate::BitReader<VCCIO_WS_VOL_MOD_SEL_A>;
60#[doc = "VCC_IO Withstand Voltage Mode Select Control\n\nValue on reset: 0"]
61#[derive(Clone, Copy, Debug, PartialEq, Eq)]
62pub enum VCCIO_WS_VOL_MOD_SEL_A {
63    #[doc = "0: `0`"]
64    ENABLE = 0,
65    #[doc = "1: `1`"]
66    DISABLE = 1,
67}
68impl From<VCCIO_WS_VOL_MOD_SEL_A> for bool {
69    #[inline(always)]
70    fn from(variant: VCCIO_WS_VOL_MOD_SEL_A) -> Self {
71        variant as u8 != 0
72    }
73}
74impl VCCIO_WS_VOL_MOD_SEL_R {
75    #[doc = "Get enumerated values variant"]
76    #[inline(always)]
77    pub const fn variant(&self) -> VCCIO_WS_VOL_MOD_SEL_A {
78        match self.bits {
79            false => VCCIO_WS_VOL_MOD_SEL_A::ENABLE,
80            true => VCCIO_WS_VOL_MOD_SEL_A::DISABLE,
81        }
82    }
83    #[doc = "`0`"]
84    #[inline(always)]
85    pub fn is_enable(&self) -> bool {
86        *self == VCCIO_WS_VOL_MOD_SEL_A::ENABLE
87    }
88    #[doc = "`1`"]
89    #[inline(always)]
90    pub fn is_disable(&self) -> bool {
91        *self == VCCIO_WS_VOL_MOD_SEL_A::DISABLE
92    }
93}
94#[doc = "Field `vccio_ws_vol_mod_sel` writer - VCC_IO Withstand Voltage Mode Select Control"]
95pub type VCCIO_WS_VOL_MOD_SEL_W<'a, REG> = crate::BitWriter<'a, REG, VCCIO_WS_VOL_MOD_SEL_A>;
96impl<'a, REG> VCCIO_WS_VOL_MOD_SEL_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99{
100    #[doc = "`0`"]
101    #[inline(always)]
102    pub fn enable(self) -> &'a mut crate::W<REG> {
103        self.variant(VCCIO_WS_VOL_MOD_SEL_A::ENABLE)
104    }
105    #[doc = "`1`"]
106    #[inline(always)]
107    pub fn disable(self) -> &'a mut crate::W<REG> {
108        self.variant(VCCIO_WS_VOL_MOD_SEL_A::DISABLE)
109    }
110}
111impl R {
112    #[doc = "VCC_PX Withstand Voltage Mode Select Control\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `vcc_pC_ws_vol_mod_sel` field"]
113    #[inline(always)]
114    pub fn vcc_p_ws_vol_mod_sel(&self, n: u8) -> VCC_P_WS_VOL_MOD_SEL_R {
115        #[allow(clippy::no_effect)]
116        [(); 5][n as usize];
117        VCC_P_WS_VOL_MOD_SEL_R::new(((self.bits >> (n + 2)) & 1) != 0)
118    }
119    #[doc = "Bit 2 - VCC_PX Withstand Voltage Mode Select Control"]
120    #[inline(always)]
121    pub fn vcc_p_c_ws_vol_mod_sel(&self) -> VCC_P_WS_VOL_MOD_SEL_R {
122        VCC_P_WS_VOL_MOD_SEL_R::new(((self.bits >> 2) & 1) != 0)
123    }
124    #[doc = "Bit 3 - VCC_PX Withstand Voltage Mode Select Control"]
125    #[inline(always)]
126    pub fn vcc_p_d_ws_vol_mod_sel(&self) -> VCC_P_WS_VOL_MOD_SEL_R {
127        VCC_P_WS_VOL_MOD_SEL_R::new(((self.bits >> 3) & 1) != 0)
128    }
129    #[doc = "Bit 4 - VCC_PX Withstand Voltage Mode Select Control"]
130    #[inline(always)]
131    pub fn vcc_p_e_ws_vol_mod_sel(&self) -> VCC_P_WS_VOL_MOD_SEL_R {
132        VCC_P_WS_VOL_MOD_SEL_R::new(((self.bits >> 4) & 1) != 0)
133    }
134    #[doc = "Bit 5 - VCC_PX Withstand Voltage Mode Select Control"]
135    #[inline(always)]
136    pub fn vcc_p_f_ws_vol_mod_sel(&self) -> VCC_P_WS_VOL_MOD_SEL_R {
137        VCC_P_WS_VOL_MOD_SEL_R::new(((self.bits >> 5) & 1) != 0)
138    }
139    #[doc = "Bit 6 - VCC_PX Withstand Voltage Mode Select Control"]
140    #[inline(always)]
141    pub fn vcc_p_g_ws_vol_mod_sel(&self) -> VCC_P_WS_VOL_MOD_SEL_R {
142        VCC_P_WS_VOL_MOD_SEL_R::new(((self.bits >> 6) & 1) != 0)
143    }
144    #[doc = "Bit 12 - VCC_IO Withstand Voltage Mode Select Control"]
145    #[inline(always)]
146    pub fn vccio_ws_vol_mod_sel(&self) -> VCCIO_WS_VOL_MOD_SEL_R {
147        VCCIO_WS_VOL_MOD_SEL_R::new(((self.bits >> 12) & 1) != 0)
148    }
149}
150impl W {
151    #[doc = "VCC_PX Withstand Voltage Mode Select Control\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `vcc_pC_ws_vol_mod_sel` field"]
152    #[inline(always)]
153    #[must_use]
154    pub fn vcc_p_ws_vol_mod_sel(&mut self, n: u8) -> VCC_P_WS_VOL_MOD_SEL_W<PIO_POW_MS_CTL_SPEC> {
155        #[allow(clippy::no_effect)]
156        [(); 5][n as usize];
157        VCC_P_WS_VOL_MOD_SEL_W::new(self, n + 2)
158    }
159    #[doc = "Bit 2 - VCC_PX Withstand Voltage Mode Select Control"]
160    #[inline(always)]
161    #[must_use]
162    pub fn vcc_p_c_ws_vol_mod_sel(&mut self) -> VCC_P_WS_VOL_MOD_SEL_W<PIO_POW_MS_CTL_SPEC> {
163        VCC_P_WS_VOL_MOD_SEL_W::new(self, 2)
164    }
165    #[doc = "Bit 3 - VCC_PX Withstand Voltage Mode Select Control"]
166    #[inline(always)]
167    #[must_use]
168    pub fn vcc_p_d_ws_vol_mod_sel(&mut self) -> VCC_P_WS_VOL_MOD_SEL_W<PIO_POW_MS_CTL_SPEC> {
169        VCC_P_WS_VOL_MOD_SEL_W::new(self, 3)
170    }
171    #[doc = "Bit 4 - VCC_PX Withstand Voltage Mode Select Control"]
172    #[inline(always)]
173    #[must_use]
174    pub fn vcc_p_e_ws_vol_mod_sel(&mut self) -> VCC_P_WS_VOL_MOD_SEL_W<PIO_POW_MS_CTL_SPEC> {
175        VCC_P_WS_VOL_MOD_SEL_W::new(self, 4)
176    }
177    #[doc = "Bit 5 - VCC_PX Withstand Voltage Mode Select Control"]
178    #[inline(always)]
179    #[must_use]
180    pub fn vcc_p_f_ws_vol_mod_sel(&mut self) -> VCC_P_WS_VOL_MOD_SEL_W<PIO_POW_MS_CTL_SPEC> {
181        VCC_P_WS_VOL_MOD_SEL_W::new(self, 5)
182    }
183    #[doc = "Bit 6 - VCC_PX Withstand Voltage Mode Select Control"]
184    #[inline(always)]
185    #[must_use]
186    pub fn vcc_p_g_ws_vol_mod_sel(&mut self) -> VCC_P_WS_VOL_MOD_SEL_W<PIO_POW_MS_CTL_SPEC> {
187        VCC_P_WS_VOL_MOD_SEL_W::new(self, 6)
188    }
189    #[doc = "Bit 12 - VCC_IO Withstand Voltage Mode Select Control"]
190    #[inline(always)]
191    #[must_use]
192    pub fn vccio_ws_vol_mod_sel(&mut self) -> VCCIO_WS_VOL_MOD_SEL_W<PIO_POW_MS_CTL_SPEC> {
193        VCCIO_WS_VOL_MOD_SEL_W::new(self, 12)
194    }
195    #[doc = r" Writes raw bits to the register."]
196    #[doc = r""]
197    #[doc = r" # Safety"]
198    #[doc = r""]
199    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
200    #[inline(always)]
201    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
202        self.bits = bits;
203        self
204    }
205}
206#[doc = "PIO Group Withstand Voltage Mode Select Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pio_pow_ms_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pio_pow_ms_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
207pub struct PIO_POW_MS_CTL_SPEC;
208impl crate::RegisterSpec for PIO_POW_MS_CTL_SPEC {
209    type Ux = u32;
210}
211#[doc = "`read()` method returns [`pio_pow_ms_ctl::R`](R) reader structure"]
212impl crate::Readable for PIO_POW_MS_CTL_SPEC {}
213#[doc = "`write(|w| ..)` method takes [`pio_pow_ms_ctl::W`](W) writer structure"]
214impl crate::Writable for PIO_POW_MS_CTL_SPEC {
215    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
216    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
217}
218#[doc = "`reset()` method sets pio_pow_ms_ctl to value 0"]
219impl crate::Resettable for PIO_POW_MS_CTL_SPEC {
220    const RESET_VALUE: Self::Ux = 0;
221}
d1_pac/gpio/pio_pow_ms_ctl.rs

d1_pac/gpio/
pio_pow_ms_ctl.rs
