d1_pac/gpio/
pg_eint_ctl.rs

1#[doc = "Register `pg_eint_ctl` reader"]
2pub type R = crate::R<PG_EINT_CTL_SPEC>;
3#[doc = "Register `pg_eint_ctl` writer"]
4pub type W = crate::W<PG_EINT_CTL_SPEC>;
5#[doc = "Field `eint_ctl[0-18]` reader - External INT Enable"]
6pub type EINT_CTL_R = crate::BitReader<EINT_CTL_A>;
7#[doc = "External INT Enable\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum EINT_CTL_A {
10    #[doc = "0: `0`"]
11    DISABLE = 0,
12    #[doc = "1: `1`"]
13    ENABLE = 1,
14}
15impl From<EINT_CTL_A> for bool {
16    #[inline(always)]
17    fn from(variant: EINT_CTL_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl EINT_CTL_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> EINT_CTL_A {
25        match self.bits {
26            false => EINT_CTL_A::DISABLE,
27            true => EINT_CTL_A::ENABLE,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_disable(&self) -> bool {
33        *self == EINT_CTL_A::DISABLE
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_enable(&self) -> bool {
38        *self == EINT_CTL_A::ENABLE
39    }
40}
41#[doc = "Field `eint_ctl[0-18]` writer - External INT Enable"]
42pub type EINT_CTL_W<'a, REG> = crate::BitWriter<'a, REG, EINT_CTL_A>;
43impl<'a, REG> EINT_CTL_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn disable(self) -> &'a mut crate::W<REG> {
50        self.variant(EINT_CTL_A::DISABLE)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn enable(self) -> &'a mut crate::W<REG> {
55        self.variant(EINT_CTL_A::ENABLE)
56    }
57}
58impl R {
59    #[doc = "External INT Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `eint0_ctl` field"]
60    #[inline(always)]
61    pub fn eint_ctl(&self, n: u8) -> EINT_CTL_R {
62        #[allow(clippy::no_effect)]
63        [(); 19][n as usize];
64        EINT_CTL_R::new(((self.bits >> n) & 1) != 0)
65    }
66    #[doc = "Bit 0 - External INT Enable"]
67    #[inline(always)]
68    pub fn eint0_ctl(&self) -> EINT_CTL_R {
69        EINT_CTL_R::new((self.bits & 1) != 0)
70    }
71    #[doc = "Bit 1 - External INT Enable"]
72    #[inline(always)]
73    pub fn eint1_ctl(&self) -> EINT_CTL_R {
74        EINT_CTL_R::new(((self.bits >> 1) & 1) != 0)
75    }
76    #[doc = "Bit 2 - External INT Enable"]
77    #[inline(always)]
78    pub fn eint2_ctl(&self) -> EINT_CTL_R {
79        EINT_CTL_R::new(((self.bits >> 2) & 1) != 0)
80    }
81    #[doc = "Bit 3 - External INT Enable"]
82    #[inline(always)]
83    pub fn eint3_ctl(&self) -> EINT_CTL_R {
84        EINT_CTL_R::new(((self.bits >> 3) & 1) != 0)
85    }
86    #[doc = "Bit 4 - External INT Enable"]
87    #[inline(always)]
88    pub fn eint4_ctl(&self) -> EINT_CTL_R {
89        EINT_CTL_R::new(((self.bits >> 4) & 1) != 0)
90    }
91    #[doc = "Bit 5 - External INT Enable"]
92    #[inline(always)]
93    pub fn eint5_ctl(&self) -> EINT_CTL_R {
94        EINT_CTL_R::new(((self.bits >> 5) & 1) != 0)
95    }
96    #[doc = "Bit 6 - External INT Enable"]
97    #[inline(always)]
98    pub fn eint6_ctl(&self) -> EINT_CTL_R {
99        EINT_CTL_R::new(((self.bits >> 6) & 1) != 0)
100    }
101    #[doc = "Bit 7 - External INT Enable"]
102    #[inline(always)]
103    pub fn eint7_ctl(&self) -> EINT_CTL_R {
104        EINT_CTL_R::new(((self.bits >> 7) & 1) != 0)
105    }
106    #[doc = "Bit 8 - External INT Enable"]
107    #[inline(always)]
108    pub fn eint8_ctl(&self) -> EINT_CTL_R {
109        EINT_CTL_R::new(((self.bits >> 8) & 1) != 0)
110    }
111    #[doc = "Bit 9 - External INT Enable"]
112    #[inline(always)]
113    pub fn eint9_ctl(&self) -> EINT_CTL_R {
114        EINT_CTL_R::new(((self.bits >> 9) & 1) != 0)
115    }
116    #[doc = "Bit 10 - External INT Enable"]
117    #[inline(always)]
118    pub fn eint10_ctl(&self) -> EINT_CTL_R {
119        EINT_CTL_R::new(((self.bits >> 10) & 1) != 0)
120    }
121    #[doc = "Bit 11 - External INT Enable"]
122    #[inline(always)]
123    pub fn eint11_ctl(&self) -> EINT_CTL_R {
124        EINT_CTL_R::new(((self.bits >> 11) & 1) != 0)
125    }
126    #[doc = "Bit 12 - External INT Enable"]
127    #[inline(always)]
128    pub fn eint12_ctl(&self) -> EINT_CTL_R {
129        EINT_CTL_R::new(((self.bits >> 12) & 1) != 0)
130    }
131    #[doc = "Bit 13 - External INT Enable"]
132    #[inline(always)]
133    pub fn eint13_ctl(&self) -> EINT_CTL_R {
134        EINT_CTL_R::new(((self.bits >> 13) & 1) != 0)
135    }
136    #[doc = "Bit 14 - External INT Enable"]
137    #[inline(always)]
138    pub fn eint14_ctl(&self) -> EINT_CTL_R {
139        EINT_CTL_R::new(((self.bits >> 14) & 1) != 0)
140    }
141    #[doc = "Bit 15 - External INT Enable"]
142    #[inline(always)]
143    pub fn eint15_ctl(&self) -> EINT_CTL_R {
144        EINT_CTL_R::new(((self.bits >> 15) & 1) != 0)
145    }
146    #[doc = "Bit 16 - External INT Enable"]
147    #[inline(always)]
148    pub fn eint16_ctl(&self) -> EINT_CTL_R {
149        EINT_CTL_R::new(((self.bits >> 16) & 1) != 0)
150    }
151    #[doc = "Bit 17 - External INT Enable"]
152    #[inline(always)]
153    pub fn eint17_ctl(&self) -> EINT_CTL_R {
154        EINT_CTL_R::new(((self.bits >> 17) & 1) != 0)
155    }
156    #[doc = "Bit 18 - External INT Enable"]
157    #[inline(always)]
158    pub fn eint18_ctl(&self) -> EINT_CTL_R {
159        EINT_CTL_R::new(((self.bits >> 18) & 1) != 0)
160    }
161}
162impl W {
163    #[doc = "External INT Enable\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `eint0_ctl` field"]
164    #[inline(always)]
165    #[must_use]
166    pub fn eint_ctl(&mut self, n: u8) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
167        #[allow(clippy::no_effect)]
168        [(); 19][n as usize];
169        EINT_CTL_W::new(self, n)
170    }
171    #[doc = "Bit 0 - External INT Enable"]
172    #[inline(always)]
173    #[must_use]
174    pub fn eint0_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
175        EINT_CTL_W::new(self, 0)
176    }
177    #[doc = "Bit 1 - External INT Enable"]
178    #[inline(always)]
179    #[must_use]
180    pub fn eint1_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
181        EINT_CTL_W::new(self, 1)
182    }
183    #[doc = "Bit 2 - External INT Enable"]
184    #[inline(always)]
185    #[must_use]
186    pub fn eint2_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
187        EINT_CTL_W::new(self, 2)
188    }
189    #[doc = "Bit 3 - External INT Enable"]
190    #[inline(always)]
191    #[must_use]
192    pub fn eint3_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
193        EINT_CTL_W::new(self, 3)
194    }
195    #[doc = "Bit 4 - External INT Enable"]
196    #[inline(always)]
197    #[must_use]
198    pub fn eint4_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
199        EINT_CTL_W::new(self, 4)
200    }
201    #[doc = "Bit 5 - External INT Enable"]
202    #[inline(always)]
203    #[must_use]
204    pub fn eint5_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
205        EINT_CTL_W::new(self, 5)
206    }
207    #[doc = "Bit 6 - External INT Enable"]
208    #[inline(always)]
209    #[must_use]
210    pub fn eint6_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
211        EINT_CTL_W::new(self, 6)
212    }
213    #[doc = "Bit 7 - External INT Enable"]
214    #[inline(always)]
215    #[must_use]
216    pub fn eint7_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
217        EINT_CTL_W::new(self, 7)
218    }
219    #[doc = "Bit 8 - External INT Enable"]
220    #[inline(always)]
221    #[must_use]
222    pub fn eint8_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
223        EINT_CTL_W::new(self, 8)
224    }
225    #[doc = "Bit 9 - External INT Enable"]
226    #[inline(always)]
227    #[must_use]
228    pub fn eint9_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
229        EINT_CTL_W::new(self, 9)
230    }
231    #[doc = "Bit 10 - External INT Enable"]
232    #[inline(always)]
233    #[must_use]
234    pub fn eint10_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
235        EINT_CTL_W::new(self, 10)
236    }
237    #[doc = "Bit 11 - External INT Enable"]
238    #[inline(always)]
239    #[must_use]
240    pub fn eint11_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
241        EINT_CTL_W::new(self, 11)
242    }
243    #[doc = "Bit 12 - External INT Enable"]
244    #[inline(always)]
245    #[must_use]
246    pub fn eint12_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
247        EINT_CTL_W::new(self, 12)
248    }
249    #[doc = "Bit 13 - External INT Enable"]
250    #[inline(always)]
251    #[must_use]
252    pub fn eint13_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
253        EINT_CTL_W::new(self, 13)
254    }
255    #[doc = "Bit 14 - External INT Enable"]
256    #[inline(always)]
257    #[must_use]
258    pub fn eint14_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
259        EINT_CTL_W::new(self, 14)
260    }
261    #[doc = "Bit 15 - External INT Enable"]
262    #[inline(always)]
263    #[must_use]
264    pub fn eint15_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
265        EINT_CTL_W::new(self, 15)
266    }
267    #[doc = "Bit 16 - External INT Enable"]
268    #[inline(always)]
269    #[must_use]
270    pub fn eint16_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
271        EINT_CTL_W::new(self, 16)
272    }
273    #[doc = "Bit 17 - External INT Enable"]
274    #[inline(always)]
275    #[must_use]
276    pub fn eint17_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
277        EINT_CTL_W::new(self, 17)
278    }
279    #[doc = "Bit 18 - External INT Enable"]
280    #[inline(always)]
281    #[must_use]
282    pub fn eint18_ctl(&mut self) -> EINT_CTL_W<PG_EINT_CTL_SPEC> {
283        EINT_CTL_W::new(self, 18)
284    }
285    #[doc = r" Writes raw bits to the register."]
286    #[doc = r""]
287    #[doc = r" # Safety"]
288    #[doc = r""]
289    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
290    #[inline(always)]
291    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
292        self.bits = bits;
293        self
294    }
295}
296#[doc = "PG External Interrupt Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pg_eint_ctl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pg_eint_ctl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
297pub struct PG_EINT_CTL_SPEC;
298impl crate::RegisterSpec for PG_EINT_CTL_SPEC {
299    type Ux = u32;
300}
301#[doc = "`read()` method returns [`pg_eint_ctl::R`](R) reader structure"]
302impl crate::Readable for PG_EINT_CTL_SPEC {}
303#[doc = "`write(|w| ..)` method takes [`pg_eint_ctl::W`](W) writer structure"]
304impl crate::Writable for PG_EINT_CTL_SPEC {
305    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
306    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
307}
308#[doc = "`reset()` method sets pg_eint_ctl to value 0"]
309impl crate::Resettable for PG_EINT_CTL_SPEC {
310    const RESET_VALUE: Self::Ux = 0;
311}
d1_pac/gpio/pg_eint_ctl.rs

d1_pac/gpio/
pg_eint_ctl.rs
