d1_pac/gpio/
pg_drv2.rs

1#[doc = "Register `pg_drv2` reader"]
2pub type R = crate::R<PG_DRV2_SPEC>;
3#[doc = "Register `pg_drv2` writer"]
4pub type W = crate::W<PG_DRV2_SPEC>;
5#[doc = "Field `pg_drv[16-18]` reader - PG Multi_Driving Select"]
6pub type PG_DRV_R = crate::FieldReader<PG_DRV_A>;
7#[doc = "PG Multi_Driving Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PG_DRV_A {
11    #[doc = "0: `0`"]
12    L0 = 0,
13    #[doc = "1: `1`"]
14    L1 = 1,
15    #[doc = "2: `10`"]
16    L2 = 2,
17    #[doc = "3: `11`"]
18    L3 = 3,
19}
20impl From<PG_DRV_A> for u8 {
21    #[inline(always)]
22    fn from(variant: PG_DRV_A) -> Self {
23        variant as _
24    }
25}
26impl crate::FieldSpec for PG_DRV_A {
27    type Ux = u8;
28}
29impl PG_DRV_R {
30    #[doc = "Get enumerated values variant"]
31    #[inline(always)]
32    pub const fn variant(&self) -> PG_DRV_A {
33        match self.bits {
34            0 => PG_DRV_A::L0,
35            1 => PG_DRV_A::L1,
36            2 => PG_DRV_A::L2,
37            3 => PG_DRV_A::L3,
38            _ => unreachable!(),
39        }
40    }
41    #[doc = "`0`"]
42    #[inline(always)]
43    pub fn is_l0(&self) -> bool {
44        *self == PG_DRV_A::L0
45    }
46    #[doc = "`1`"]
47    #[inline(always)]
48    pub fn is_l1(&self) -> bool {
49        *self == PG_DRV_A::L1
50    }
51    #[doc = "`10`"]
52    #[inline(always)]
53    pub fn is_l2(&self) -> bool {
54        *self == PG_DRV_A::L2
55    }
56    #[doc = "`11`"]
57    #[inline(always)]
58    pub fn is_l3(&self) -> bool {
59        *self == PG_DRV_A::L3
60    }
61}
62#[doc = "Field `pg_drv[16-18]` writer - PG Multi_Driving Select"]
63pub type PG_DRV_W<'a, REG> = crate::FieldWriterSafe<'a, REG, 2, PG_DRV_A>;
64impl<'a, REG> PG_DRV_W<'a, REG>
65where
66    REG: crate::Writable + crate::RegisterSpec,
67    REG::Ux: From<u8>,
68{
69    #[doc = "`0`"]
70    #[inline(always)]
71    pub fn l0(self) -> &'a mut crate::W<REG> {
72        self.variant(PG_DRV_A::L0)
73    }
74    #[doc = "`1`"]
75    #[inline(always)]
76    pub fn l1(self) -> &'a mut crate::W<REG> {
77        self.variant(PG_DRV_A::L1)
78    }
79    #[doc = "`10`"]
80    #[inline(always)]
81    pub fn l2(self) -> &'a mut crate::W<REG> {
82        self.variant(PG_DRV_A::L2)
83    }
84    #[doc = "`11`"]
85    #[inline(always)]
86    pub fn l3(self) -> &'a mut crate::W<REG> {
87        self.variant(PG_DRV_A::L3)
88    }
89}
90impl R {
91    #[doc = "PG Multi_Driving Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pg16_drv` field"]
92    #[inline(always)]
93    pub fn pg_drv(&self, n: u8) -> PG_DRV_R {
94        #[allow(clippy::no_effect)]
95        [(); 3][n as usize];
96        PG_DRV_R::new(((self.bits >> (n * 4)) & 3) as u8)
97    }
98    #[doc = "Bits 0:1 - PG Multi_Driving Select"]
99    #[inline(always)]
100    pub fn pg16_drv(&self) -> PG_DRV_R {
101        PG_DRV_R::new((self.bits & 3) as u8)
102    }
103    #[doc = "Bits 4:5 - PG Multi_Driving Select"]
104    #[inline(always)]
105    pub fn pg17_drv(&self) -> PG_DRV_R {
106        PG_DRV_R::new(((self.bits >> 4) & 3) as u8)
107    }
108    #[doc = "Bits 8:9 - PG Multi_Driving Select"]
109    #[inline(always)]
110    pub fn pg18_drv(&self) -> PG_DRV_R {
111        PG_DRV_R::new(((self.bits >> 8) & 3) as u8)
112    }
113}
114impl W {
115    #[doc = "PG Multi_Driving Select\n\nNOTE: `n` is number of field in register. `n == 0` corresponds to `pg16_drv` field"]
116    #[inline(always)]
117    #[must_use]
118    pub fn pg_drv(&mut self, n: u8) -> PG_DRV_W<PG_DRV2_SPEC> {
119        #[allow(clippy::no_effect)]
120        [(); 3][n as usize];
121        PG_DRV_W::new(self, n * 4)
122    }
123    #[doc = "Bits 0:1 - PG Multi_Driving Select"]
124    #[inline(always)]
125    #[must_use]
126    pub fn pg16_drv(&mut self) -> PG_DRV_W<PG_DRV2_SPEC> {
127        PG_DRV_W::new(self, 0)
128    }
129    #[doc = "Bits 4:5 - PG Multi_Driving Select"]
130    #[inline(always)]
131    #[must_use]
132    pub fn pg17_drv(&mut self) -> PG_DRV_W<PG_DRV2_SPEC> {
133        PG_DRV_W::new(self, 4)
134    }
135    #[doc = "Bits 8:9 - PG Multi_Driving Select"]
136    #[inline(always)]
137    #[must_use]
138    pub fn pg18_drv(&mut self) -> PG_DRV_W<PG_DRV2_SPEC> {
139        PG_DRV_W::new(self, 8)
140    }
141    #[doc = r" Writes raw bits to the register."]
142    #[doc = r""]
143    #[doc = r" # Safety"]
144    #[doc = r""]
145    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
146    #[inline(always)]
147    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
148        self.bits = bits;
149        self
150    }
151}
152#[doc = "PG Multi_Driving Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pg_drv2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pg_drv2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
153pub struct PG_DRV2_SPEC;
154impl crate::RegisterSpec for PG_DRV2_SPEC {
155    type Ux = u32;
156}
157#[doc = "`read()` method returns [`pg_drv2::R`](R) reader structure"]
158impl crate::Readable for PG_DRV2_SPEC {}
159#[doc = "`write(|w| ..)` method takes [`pg_drv2::W`](W) writer structure"]
160impl crate::Writable for PG_DRV2_SPEC {
161    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
162    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
163}
164#[doc = "`reset()` method sets pg_drv2 to value 0"]
165impl crate::Resettable for PG_DRV2_SPEC {
166    const RESET_VALUE: Self::Ux = 0;
167}
d1_pac/gpio/pg_drv2.rs

d1_pac/gpio/
pg_drv2.rs
