d1_pac/gpio/
pg_cfg2.rs

1#[doc = "Register `pg_cfg2` reader"]
2pub type R = crate::R<PG_CFG2_SPEC>;
3#[doc = "Register `pg_cfg2` writer"]
4pub type W = crate::W<PG_CFG2_SPEC>;
5#[doc = "Field `pg16_select` reader - PG16 Select"]
6pub type PG16_SELECT_R = crate::FieldReader<PG16_SELECT_A>;
7#[doc = "PG16 Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PG16_SELECT_A {
11    #[doc = "0: `0`"]
12    INPUT = 0,
13    #[doc = "2: `10`"]
14    IR_RX = 2,
15    #[doc = "4: `100`"]
16    PWM5 = 4,
17    #[doc = "6: `110`"]
18    OWA_IN = 6,
19    #[doc = "14: `1110`"]
20    PG_EINT16 = 14,
21    #[doc = "1: `1`"]
22    OUTPUT = 1,
23    #[doc = "3: `11`"]
24    TCON_TRIG = 3,
25    #[doc = "5: `101`"]
26    CLK_FANOUT2 = 5,
27    #[doc = "7: `111`"]
28    LEDC_DO = 7,
29    #[doc = "15: `1111`"]
30    IO_DISABLE = 15,
31}
32impl From<PG16_SELECT_A> for u8 {
33    #[inline(always)]
34    fn from(variant: PG16_SELECT_A) -> Self {
35        variant as _
36    }
37}
38impl crate::FieldSpec for PG16_SELECT_A {
39    type Ux = u8;
40}
41impl PG16_SELECT_R {
42    #[doc = "Get enumerated values variant"]
43    #[inline(always)]
44    pub const fn variant(&self) -> Option<PG16_SELECT_A> {
45        match self.bits {
46            0 => Some(PG16_SELECT_A::INPUT),
47            2 => Some(PG16_SELECT_A::IR_RX),
48            4 => Some(PG16_SELECT_A::PWM5),
49            6 => Some(PG16_SELECT_A::OWA_IN),
50            14 => Some(PG16_SELECT_A::PG_EINT16),
51            1 => Some(PG16_SELECT_A::OUTPUT),
52            3 => Some(PG16_SELECT_A::TCON_TRIG),
53            5 => Some(PG16_SELECT_A::CLK_FANOUT2),
54            7 => Some(PG16_SELECT_A::LEDC_DO),
55            15 => Some(PG16_SELECT_A::IO_DISABLE),
56            _ => None,
57        }
58    }
59    #[doc = "`0`"]
60    #[inline(always)]
61    pub fn is_input(&self) -> bool {
62        *self == PG16_SELECT_A::INPUT
63    }
64    #[doc = "`10`"]
65    #[inline(always)]
66    pub fn is_ir_rx(&self) -> bool {
67        *self == PG16_SELECT_A::IR_RX
68    }
69    #[doc = "`100`"]
70    #[inline(always)]
71    pub fn is_pwm5(&self) -> bool {
72        *self == PG16_SELECT_A::PWM5
73    }
74    #[doc = "`110`"]
75    #[inline(always)]
76    pub fn is_owa_in(&self) -> bool {
77        *self == PG16_SELECT_A::OWA_IN
78    }
79    #[doc = "`1110`"]
80    #[inline(always)]
81    pub fn is_pg_eint16(&self) -> bool {
82        *self == PG16_SELECT_A::PG_EINT16
83    }
84    #[doc = "`1`"]
85    #[inline(always)]
86    pub fn is_output(&self) -> bool {
87        *self == PG16_SELECT_A::OUTPUT
88    }
89    #[doc = "`11`"]
90    #[inline(always)]
91    pub fn is_tcon_trig(&self) -> bool {
92        *self == PG16_SELECT_A::TCON_TRIG
93    }
94    #[doc = "`101`"]
95    #[inline(always)]
96    pub fn is_clk_fanout2(&self) -> bool {
97        *self == PG16_SELECT_A::CLK_FANOUT2
98    }
99    #[doc = "`111`"]
100    #[inline(always)]
101    pub fn is_ledc_do(&self) -> bool {
102        *self == PG16_SELECT_A::LEDC_DO
103    }
104    #[doc = "`1111`"]
105    #[inline(always)]
106    pub fn is_io_disable(&self) -> bool {
107        *self == PG16_SELECT_A::IO_DISABLE
108    }
109}
110#[doc = "Field `pg16_select` writer - PG16 Select"]
111pub type PG16_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG16_SELECT_A>;
112impl<'a, REG> PG16_SELECT_W<'a, REG>
113where
114    REG: crate::Writable + crate::RegisterSpec,
115    REG::Ux: From<u8>,
116{
117    #[doc = "`0`"]
118    #[inline(always)]
119    pub fn input(self) -> &'a mut crate::W<REG> {
120        self.variant(PG16_SELECT_A::INPUT)
121    }
122    #[doc = "`10`"]
123    #[inline(always)]
124    pub fn ir_rx(self) -> &'a mut crate::W<REG> {
125        self.variant(PG16_SELECT_A::IR_RX)
126    }
127    #[doc = "`100`"]
128    #[inline(always)]
129    pub fn pwm5(self) -> &'a mut crate::W<REG> {
130        self.variant(PG16_SELECT_A::PWM5)
131    }
132    #[doc = "`110`"]
133    #[inline(always)]
134    pub fn owa_in(self) -> &'a mut crate::W<REG> {
135        self.variant(PG16_SELECT_A::OWA_IN)
136    }
137    #[doc = "`1110`"]
138    #[inline(always)]
139    pub fn pg_eint16(self) -> &'a mut crate::W<REG> {
140        self.variant(PG16_SELECT_A::PG_EINT16)
141    }
142    #[doc = "`1`"]
143    #[inline(always)]
144    pub fn output(self) -> &'a mut crate::W<REG> {
145        self.variant(PG16_SELECT_A::OUTPUT)
146    }
147    #[doc = "`11`"]
148    #[inline(always)]
149    pub fn tcon_trig(self) -> &'a mut crate::W<REG> {
150        self.variant(PG16_SELECT_A::TCON_TRIG)
151    }
152    #[doc = "`101`"]
153    #[inline(always)]
154    pub fn clk_fanout2(self) -> &'a mut crate::W<REG> {
155        self.variant(PG16_SELECT_A::CLK_FANOUT2)
156    }
157    #[doc = "`111`"]
158    #[inline(always)]
159    pub fn ledc_do(self) -> &'a mut crate::W<REG> {
160        self.variant(PG16_SELECT_A::LEDC_DO)
161    }
162    #[doc = "`1111`"]
163    #[inline(always)]
164    pub fn io_disable(self) -> &'a mut crate::W<REG> {
165        self.variant(PG16_SELECT_A::IO_DISABLE)
166    }
167}
168#[doc = "Field `pg17_select` reader - PG17 Select"]
169pub type PG17_SELECT_R = crate::FieldReader<PG17_SELECT_A>;
170#[doc = "PG17 Select\n\nValue on reset: 0"]
171#[derive(Clone, Copy, Debug, PartialEq, Eq)]
172#[repr(u8)]
173pub enum PG17_SELECT_A {
174    #[doc = "0: `0`"]
175    INPUT = 0,
176    #[doc = "2: `10`"]
177    UART2_TX = 2,
178    #[doc = "4: `100`"]
179    PWM7 = 4,
180    #[doc = "6: `110`"]
181    IR_TX = 6,
182    #[doc = "14: `1110`"]
183    PG_EINT17 = 14,
184    #[doc = "1: `1`"]
185    OUTPUT = 1,
186    #[doc = "3: `11`"]
187    TWI3_SCK = 3,
188    #[doc = "5: `101`"]
189    CLK_FANOUT0 = 5,
190    #[doc = "7: `111`"]
191    UART0_TX = 7,
192    #[doc = "15: `1111`"]
193    IO_DISABLE = 15,
194}
195impl From<PG17_SELECT_A> for u8 {
196    #[inline(always)]
197    fn from(variant: PG17_SELECT_A) -> Self {
198        variant as _
199    }
200}
201impl crate::FieldSpec for PG17_SELECT_A {
202    type Ux = u8;
203}
204impl PG17_SELECT_R {
205    #[doc = "Get enumerated values variant"]
206    #[inline(always)]
207    pub const fn variant(&self) -> Option<PG17_SELECT_A> {
208        match self.bits {
209            0 => Some(PG17_SELECT_A::INPUT),
210            2 => Some(PG17_SELECT_A::UART2_TX),
211            4 => Some(PG17_SELECT_A::PWM7),
212            6 => Some(PG17_SELECT_A::IR_TX),
213            14 => Some(PG17_SELECT_A::PG_EINT17),
214            1 => Some(PG17_SELECT_A::OUTPUT),
215            3 => Some(PG17_SELECT_A::TWI3_SCK),
216            5 => Some(PG17_SELECT_A::CLK_FANOUT0),
217            7 => Some(PG17_SELECT_A::UART0_TX),
218            15 => Some(PG17_SELECT_A::IO_DISABLE),
219            _ => None,
220        }
221    }
222    #[doc = "`0`"]
223    #[inline(always)]
224    pub fn is_input(&self) -> bool {
225        *self == PG17_SELECT_A::INPUT
226    }
227    #[doc = "`10`"]
228    #[inline(always)]
229    pub fn is_uart2_tx(&self) -> bool {
230        *self == PG17_SELECT_A::UART2_TX
231    }
232    #[doc = "`100`"]
233    #[inline(always)]
234    pub fn is_pwm7(&self) -> bool {
235        *self == PG17_SELECT_A::PWM7
236    }
237    #[doc = "`110`"]
238    #[inline(always)]
239    pub fn is_ir_tx(&self) -> bool {
240        *self == PG17_SELECT_A::IR_TX
241    }
242    #[doc = "`1110`"]
243    #[inline(always)]
244    pub fn is_pg_eint17(&self) -> bool {
245        *self == PG17_SELECT_A::PG_EINT17
246    }
247    #[doc = "`1`"]
248    #[inline(always)]
249    pub fn is_output(&self) -> bool {
250        *self == PG17_SELECT_A::OUTPUT
251    }
252    #[doc = "`11`"]
253    #[inline(always)]
254    pub fn is_twi3_sck(&self) -> bool {
255        *self == PG17_SELECT_A::TWI3_SCK
256    }
257    #[doc = "`101`"]
258    #[inline(always)]
259    pub fn is_clk_fanout0(&self) -> bool {
260        *self == PG17_SELECT_A::CLK_FANOUT0
261    }
262    #[doc = "`111`"]
263    #[inline(always)]
264    pub fn is_uart0_tx(&self) -> bool {
265        *self == PG17_SELECT_A::UART0_TX
266    }
267    #[doc = "`1111`"]
268    #[inline(always)]
269    pub fn is_io_disable(&self) -> bool {
270        *self == PG17_SELECT_A::IO_DISABLE
271    }
272}
273#[doc = "Field `pg17_select` writer - PG17 Select"]
274pub type PG17_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG17_SELECT_A>;
275impl<'a, REG> PG17_SELECT_W<'a, REG>
276where
277    REG: crate::Writable + crate::RegisterSpec,
278    REG::Ux: From<u8>,
279{
280    #[doc = "`0`"]
281    #[inline(always)]
282    pub fn input(self) -> &'a mut crate::W<REG> {
283        self.variant(PG17_SELECT_A::INPUT)
284    }
285    #[doc = "`10`"]
286    #[inline(always)]
287    pub fn uart2_tx(self) -> &'a mut crate::W<REG> {
288        self.variant(PG17_SELECT_A::UART2_TX)
289    }
290    #[doc = "`100`"]
291    #[inline(always)]
292    pub fn pwm7(self) -> &'a mut crate::W<REG> {
293        self.variant(PG17_SELECT_A::PWM7)
294    }
295    #[doc = "`110`"]
296    #[inline(always)]
297    pub fn ir_tx(self) -> &'a mut crate::W<REG> {
298        self.variant(PG17_SELECT_A::IR_TX)
299    }
300    #[doc = "`1110`"]
301    #[inline(always)]
302    pub fn pg_eint17(self) -> &'a mut crate::W<REG> {
303        self.variant(PG17_SELECT_A::PG_EINT17)
304    }
305    #[doc = "`1`"]
306    #[inline(always)]
307    pub fn output(self) -> &'a mut crate::W<REG> {
308        self.variant(PG17_SELECT_A::OUTPUT)
309    }
310    #[doc = "`11`"]
311    #[inline(always)]
312    pub fn twi3_sck(self) -> &'a mut crate::W<REG> {
313        self.variant(PG17_SELECT_A::TWI3_SCK)
314    }
315    #[doc = "`101`"]
316    #[inline(always)]
317    pub fn clk_fanout0(self) -> &'a mut crate::W<REG> {
318        self.variant(PG17_SELECT_A::CLK_FANOUT0)
319    }
320    #[doc = "`111`"]
321    #[inline(always)]
322    pub fn uart0_tx(self) -> &'a mut crate::W<REG> {
323        self.variant(PG17_SELECT_A::UART0_TX)
324    }
325    #[doc = "`1111`"]
326    #[inline(always)]
327    pub fn io_disable(self) -> &'a mut crate::W<REG> {
328        self.variant(PG17_SELECT_A::IO_DISABLE)
329    }
330}
331#[doc = "Field `pg18_select` reader - PG18 Select"]
332pub type PG18_SELECT_R = crate::FieldReader<PG18_SELECT_A>;
333#[doc = "PG18 Select\n\nValue on reset: 0"]
334#[derive(Clone, Copy, Debug, PartialEq, Eq)]
335#[repr(u8)]
336pub enum PG18_SELECT_A {
337    #[doc = "0: `0`"]
338    INPUT = 0,
339    #[doc = "2: `10`"]
340    UART2_RX = 2,
341    #[doc = "4: `100`"]
342    PWM6 = 4,
343    #[doc = "6: `110`"]
344    OWA_OUT = 6,
345    #[doc = "14: `1110`"]
346    PG_EINT18 = 14,
347    #[doc = "1: `1`"]
348    OUTPUT = 1,
349    #[doc = "3: `11`"]
350    TWI3_SDA = 3,
351    #[doc = "5: `101`"]
352    CLK_FANOUT1 = 5,
353    #[doc = "7: `111`"]
354    UART0_RX = 7,
355    #[doc = "15: `1111`"]
356    IO_DISABLE = 15,
357}
358impl From<PG18_SELECT_A> for u8 {
359    #[inline(always)]
360    fn from(variant: PG18_SELECT_A) -> Self {
361        variant as _
362    }
363}
364impl crate::FieldSpec for PG18_SELECT_A {
365    type Ux = u8;
366}
367impl PG18_SELECT_R {
368    #[doc = "Get enumerated values variant"]
369    #[inline(always)]
370    pub const fn variant(&self) -> Option<PG18_SELECT_A> {
371        match self.bits {
372            0 => Some(PG18_SELECT_A::INPUT),
373            2 => Some(PG18_SELECT_A::UART2_RX),
374            4 => Some(PG18_SELECT_A::PWM6),
375            6 => Some(PG18_SELECT_A::OWA_OUT),
376            14 => Some(PG18_SELECT_A::PG_EINT18),
377            1 => Some(PG18_SELECT_A::OUTPUT),
378            3 => Some(PG18_SELECT_A::TWI3_SDA),
379            5 => Some(PG18_SELECT_A::CLK_FANOUT1),
380            7 => Some(PG18_SELECT_A::UART0_RX),
381            15 => Some(PG18_SELECT_A::IO_DISABLE),
382            _ => None,
383        }
384    }
385    #[doc = "`0`"]
386    #[inline(always)]
387    pub fn is_input(&self) -> bool {
388        *self == PG18_SELECT_A::INPUT
389    }
390    #[doc = "`10`"]
391    #[inline(always)]
392    pub fn is_uart2_rx(&self) -> bool {
393        *self == PG18_SELECT_A::UART2_RX
394    }
395    #[doc = "`100`"]
396    #[inline(always)]
397    pub fn is_pwm6(&self) -> bool {
398        *self == PG18_SELECT_A::PWM6
399    }
400    #[doc = "`110`"]
401    #[inline(always)]
402    pub fn is_owa_out(&self) -> bool {
403        *self == PG18_SELECT_A::OWA_OUT
404    }
405    #[doc = "`1110`"]
406    #[inline(always)]
407    pub fn is_pg_eint18(&self) -> bool {
408        *self == PG18_SELECT_A::PG_EINT18
409    }
410    #[doc = "`1`"]
411    #[inline(always)]
412    pub fn is_output(&self) -> bool {
413        *self == PG18_SELECT_A::OUTPUT
414    }
415    #[doc = "`11`"]
416    #[inline(always)]
417    pub fn is_twi3_sda(&self) -> bool {
418        *self == PG18_SELECT_A::TWI3_SDA
419    }
420    #[doc = "`101`"]
421    #[inline(always)]
422    pub fn is_clk_fanout1(&self) -> bool {
423        *self == PG18_SELECT_A::CLK_FANOUT1
424    }
425    #[doc = "`111`"]
426    #[inline(always)]
427    pub fn is_uart0_rx(&self) -> bool {
428        *self == PG18_SELECT_A::UART0_RX
429    }
430    #[doc = "`1111`"]
431    #[inline(always)]
432    pub fn is_io_disable(&self) -> bool {
433        *self == PG18_SELECT_A::IO_DISABLE
434    }
435}
436#[doc = "Field `pg18_select` writer - PG18 Select"]
437pub type PG18_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG18_SELECT_A>;
438impl<'a, REG> PG18_SELECT_W<'a, REG>
439where
440    REG: crate::Writable + crate::RegisterSpec,
441    REG::Ux: From<u8>,
442{
443    #[doc = "`0`"]
444    #[inline(always)]
445    pub fn input(self) -> &'a mut crate::W<REG> {
446        self.variant(PG18_SELECT_A::INPUT)
447    }
448    #[doc = "`10`"]
449    #[inline(always)]
450    pub fn uart2_rx(self) -> &'a mut crate::W<REG> {
451        self.variant(PG18_SELECT_A::UART2_RX)
452    }
453    #[doc = "`100`"]
454    #[inline(always)]
455    pub fn pwm6(self) -> &'a mut crate::W<REG> {
456        self.variant(PG18_SELECT_A::PWM6)
457    }
458    #[doc = "`110`"]
459    #[inline(always)]
460    pub fn owa_out(self) -> &'a mut crate::W<REG> {
461        self.variant(PG18_SELECT_A::OWA_OUT)
462    }
463    #[doc = "`1110`"]
464    #[inline(always)]
465    pub fn pg_eint18(self) -> &'a mut crate::W<REG> {
466        self.variant(PG18_SELECT_A::PG_EINT18)
467    }
468    #[doc = "`1`"]
469    #[inline(always)]
470    pub fn output(self) -> &'a mut crate::W<REG> {
471        self.variant(PG18_SELECT_A::OUTPUT)
472    }
473    #[doc = "`11`"]
474    #[inline(always)]
475    pub fn twi3_sda(self) -> &'a mut crate::W<REG> {
476        self.variant(PG18_SELECT_A::TWI3_SDA)
477    }
478    #[doc = "`101`"]
479    #[inline(always)]
480    pub fn clk_fanout1(self) -> &'a mut crate::W<REG> {
481        self.variant(PG18_SELECT_A::CLK_FANOUT1)
482    }
483    #[doc = "`111`"]
484    #[inline(always)]
485    pub fn uart0_rx(self) -> &'a mut crate::W<REG> {
486        self.variant(PG18_SELECT_A::UART0_RX)
487    }
488    #[doc = "`1111`"]
489    #[inline(always)]
490    pub fn io_disable(self) -> &'a mut crate::W<REG> {
491        self.variant(PG18_SELECT_A::IO_DISABLE)
492    }
493}
494impl R {
495    #[doc = "Bits 0:3 - PG16 Select"]
496    #[inline(always)]
497    pub fn pg16_select(&self) -> PG16_SELECT_R {
498        PG16_SELECT_R::new((self.bits & 0x0f) as u8)
499    }
500    #[doc = "Bits 4:7 - PG17 Select"]
501    #[inline(always)]
502    pub fn pg17_select(&self) -> PG17_SELECT_R {
503        PG17_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
504    }
505    #[doc = "Bits 8:11 - PG18 Select"]
506    #[inline(always)]
507    pub fn pg18_select(&self) -> PG18_SELECT_R {
508        PG18_SELECT_R::new(((self.bits >> 8) & 0x0f) as u8)
509    }
510}
511impl W {
512    #[doc = "Bits 0:3 - PG16 Select"]
513    #[inline(always)]
514    #[must_use]
515    pub fn pg16_select(&mut self) -> PG16_SELECT_W<PG_CFG2_SPEC> {
516        PG16_SELECT_W::new(self, 0)
517    }
518    #[doc = "Bits 4:7 - PG17 Select"]
519    #[inline(always)]
520    #[must_use]
521    pub fn pg17_select(&mut self) -> PG17_SELECT_W<PG_CFG2_SPEC> {
522        PG17_SELECT_W::new(self, 4)
523    }
524    #[doc = "Bits 8:11 - PG18 Select"]
525    #[inline(always)]
526    #[must_use]
527    pub fn pg18_select(&mut self) -> PG18_SELECT_W<PG_CFG2_SPEC> {
528        PG18_SELECT_W::new(self, 8)
529    }
530    #[doc = r" Writes raw bits to the register."]
531    #[doc = r""]
532    #[doc = r" # Safety"]
533    #[doc = r""]
534    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
535    #[inline(always)]
536    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
537        self.bits = bits;
538        self
539    }
540}
541#[doc = "PG Configure Register 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pg_cfg2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pg_cfg2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
542pub struct PG_CFG2_SPEC;
543impl crate::RegisterSpec for PG_CFG2_SPEC {
544    type Ux = u32;
545}
546#[doc = "`read()` method returns [`pg_cfg2::R`](R) reader structure"]
547impl crate::Readable for PG_CFG2_SPEC {}
548#[doc = "`write(|w| ..)` method takes [`pg_cfg2::W`](W) writer structure"]
549impl crate::Writable for PG_CFG2_SPEC {
550    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
551    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
552}
553#[doc = "`reset()` method sets pg_cfg2 to value 0"]
554impl crate::Resettable for PG_CFG2_SPEC {
555    const RESET_VALUE: Self::Ux = 0;
556}
d1_pac/gpio/pg_cfg2.rs

d1_pac/gpio/
pg_cfg2.rs
