d1_pac/gpio/
pg_cfg1.rs

1#[doc = "Register `pg_cfg1` reader"]
2pub type R = crate::R<PG_CFG1_SPEC>;
3#[doc = "Register `pg_cfg1` writer"]
4pub type W = crate::W<PG_CFG1_SPEC>;
5#[doc = "Field `pg8_select` reader - PG8 Select"]
6pub type PG8_SELECT_R = crate::FieldReader<PG8_SELECT_A>;
7#[doc = "PG8 Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PG8_SELECT_A {
11    #[doc = "0: `0`"]
12    INPUT = 0,
13    #[doc = "2: `10`"]
14    UART1_RTS = 2,
15    #[doc = "4: `100`"]
16    RGMII_RXD2 = 4,
17    #[doc = "14: `1110`"]
18    PG_EINT8 = 14,
19    #[doc = "1: `1`"]
20    OUTPUT = 1,
21    #[doc = "3: `11`"]
22    TWI1_SCK = 3,
23    #[doc = "5: `101`"]
24    UART3_TX = 5,
25    #[doc = "15: `1111`"]
26    IO_DISABLE = 15,
27}
28impl From<PG8_SELECT_A> for u8 {
29    #[inline(always)]
30    fn from(variant: PG8_SELECT_A) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for PG8_SELECT_A {
35    type Ux = u8;
36}
37impl PG8_SELECT_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<PG8_SELECT_A> {
41        match self.bits {
42            0 => Some(PG8_SELECT_A::INPUT),
43            2 => Some(PG8_SELECT_A::UART1_RTS),
44            4 => Some(PG8_SELECT_A::RGMII_RXD2),
45            14 => Some(PG8_SELECT_A::PG_EINT8),
46            1 => Some(PG8_SELECT_A::OUTPUT),
47            3 => Some(PG8_SELECT_A::TWI1_SCK),
48            5 => Some(PG8_SELECT_A::UART3_TX),
49            15 => Some(PG8_SELECT_A::IO_DISABLE),
50            _ => None,
51        }
52    }
53    #[doc = "`0`"]
54    #[inline(always)]
55    pub fn is_input(&self) -> bool {
56        *self == PG8_SELECT_A::INPUT
57    }
58    #[doc = "`10`"]
59    #[inline(always)]
60    pub fn is_uart1_rts(&self) -> bool {
61        *self == PG8_SELECT_A::UART1_RTS
62    }
63    #[doc = "`100`"]
64    #[inline(always)]
65    pub fn is_rgmii_rxd2(&self) -> bool {
66        *self == PG8_SELECT_A::RGMII_RXD2
67    }
68    #[doc = "`1110`"]
69    #[inline(always)]
70    pub fn is_pg_eint8(&self) -> bool {
71        *self == PG8_SELECT_A::PG_EINT8
72    }
73    #[doc = "`1`"]
74    #[inline(always)]
75    pub fn is_output(&self) -> bool {
76        *self == PG8_SELECT_A::OUTPUT
77    }
78    #[doc = "`11`"]
79    #[inline(always)]
80    pub fn is_twi1_sck(&self) -> bool {
81        *self == PG8_SELECT_A::TWI1_SCK
82    }
83    #[doc = "`101`"]
84    #[inline(always)]
85    pub fn is_uart3_tx(&self) -> bool {
86        *self == PG8_SELECT_A::UART3_TX
87    }
88    #[doc = "`1111`"]
89    #[inline(always)]
90    pub fn is_io_disable(&self) -> bool {
91        *self == PG8_SELECT_A::IO_DISABLE
92    }
93}
94#[doc = "Field `pg8_select` writer - PG8 Select"]
95pub type PG8_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG8_SELECT_A>;
96impl<'a, REG> PG8_SELECT_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99    REG::Ux: From<u8>,
100{
101    #[doc = "`0`"]
102    #[inline(always)]
103    pub fn input(self) -> &'a mut crate::W<REG> {
104        self.variant(PG8_SELECT_A::INPUT)
105    }
106    #[doc = "`10`"]
107    #[inline(always)]
108    pub fn uart1_rts(self) -> &'a mut crate::W<REG> {
109        self.variant(PG8_SELECT_A::UART1_RTS)
110    }
111    #[doc = "`100`"]
112    #[inline(always)]
113    pub fn rgmii_rxd2(self) -> &'a mut crate::W<REG> {
114        self.variant(PG8_SELECT_A::RGMII_RXD2)
115    }
116    #[doc = "`1110`"]
117    #[inline(always)]
118    pub fn pg_eint8(self) -> &'a mut crate::W<REG> {
119        self.variant(PG8_SELECT_A::PG_EINT8)
120    }
121    #[doc = "`1`"]
122    #[inline(always)]
123    pub fn output(self) -> &'a mut crate::W<REG> {
124        self.variant(PG8_SELECT_A::OUTPUT)
125    }
126    #[doc = "`11`"]
127    #[inline(always)]
128    pub fn twi1_sck(self) -> &'a mut crate::W<REG> {
129        self.variant(PG8_SELECT_A::TWI1_SCK)
130    }
131    #[doc = "`101`"]
132    #[inline(always)]
133    pub fn uart3_tx(self) -> &'a mut crate::W<REG> {
134        self.variant(PG8_SELECT_A::UART3_TX)
135    }
136    #[doc = "`1111`"]
137    #[inline(always)]
138    pub fn io_disable(self) -> &'a mut crate::W<REG> {
139        self.variant(PG8_SELECT_A::IO_DISABLE)
140    }
141}
142#[doc = "Field `pg9_select` reader - PG9 Select"]
143pub type PG9_SELECT_R = crate::FieldReader<PG9_SELECT_A>;
144#[doc = "PG9 Select\n\nValue on reset: 0"]
145#[derive(Clone, Copy, Debug, PartialEq, Eq)]
146#[repr(u8)]
147pub enum PG9_SELECT_A {
148    #[doc = "0: `0`"]
149    INPUT = 0,
150    #[doc = "2: `10`"]
151    UART1_CTS = 2,
152    #[doc = "4: `100`"]
153    RGMII_RXD3 = 4,
154    #[doc = "14: `1110`"]
155    PG_EINT9 = 14,
156    #[doc = "1: `1`"]
157    OUTPUT = 1,
158    #[doc = "3: `11`"]
159    TWI1_SDA = 3,
160    #[doc = "5: `101`"]
161    UART3_RX = 5,
162    #[doc = "15: `1111`"]
163    IO_DISABLE = 15,
164}
165impl From<PG9_SELECT_A> for u8 {
166    #[inline(always)]
167    fn from(variant: PG9_SELECT_A) -> Self {
168        variant as _
169    }
170}
171impl crate::FieldSpec for PG9_SELECT_A {
172    type Ux = u8;
173}
174impl PG9_SELECT_R {
175    #[doc = "Get enumerated values variant"]
176    #[inline(always)]
177    pub const fn variant(&self) -> Option<PG9_SELECT_A> {
178        match self.bits {
179            0 => Some(PG9_SELECT_A::INPUT),
180            2 => Some(PG9_SELECT_A::UART1_CTS),
181            4 => Some(PG9_SELECT_A::RGMII_RXD3),
182            14 => Some(PG9_SELECT_A::PG_EINT9),
183            1 => Some(PG9_SELECT_A::OUTPUT),
184            3 => Some(PG9_SELECT_A::TWI1_SDA),
185            5 => Some(PG9_SELECT_A::UART3_RX),
186            15 => Some(PG9_SELECT_A::IO_DISABLE),
187            _ => None,
188        }
189    }
190    #[doc = "`0`"]
191    #[inline(always)]
192    pub fn is_input(&self) -> bool {
193        *self == PG9_SELECT_A::INPUT
194    }
195    #[doc = "`10`"]
196    #[inline(always)]
197    pub fn is_uart1_cts(&self) -> bool {
198        *self == PG9_SELECT_A::UART1_CTS
199    }
200    #[doc = "`100`"]
201    #[inline(always)]
202    pub fn is_rgmii_rxd3(&self) -> bool {
203        *self == PG9_SELECT_A::RGMII_RXD3
204    }
205    #[doc = "`1110`"]
206    #[inline(always)]
207    pub fn is_pg_eint9(&self) -> bool {
208        *self == PG9_SELECT_A::PG_EINT9
209    }
210    #[doc = "`1`"]
211    #[inline(always)]
212    pub fn is_output(&self) -> bool {
213        *self == PG9_SELECT_A::OUTPUT
214    }
215    #[doc = "`11`"]
216    #[inline(always)]
217    pub fn is_twi1_sda(&self) -> bool {
218        *self == PG9_SELECT_A::TWI1_SDA
219    }
220    #[doc = "`101`"]
221    #[inline(always)]
222    pub fn is_uart3_rx(&self) -> bool {
223        *self == PG9_SELECT_A::UART3_RX
224    }
225    #[doc = "`1111`"]
226    #[inline(always)]
227    pub fn is_io_disable(&self) -> bool {
228        *self == PG9_SELECT_A::IO_DISABLE
229    }
230}
231#[doc = "Field `pg9_select` writer - PG9 Select"]
232pub type PG9_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG9_SELECT_A>;
233impl<'a, REG> PG9_SELECT_W<'a, REG>
234where
235    REG: crate::Writable + crate::RegisterSpec,
236    REG::Ux: From<u8>,
237{
238    #[doc = "`0`"]
239    #[inline(always)]
240    pub fn input(self) -> &'a mut crate::W<REG> {
241        self.variant(PG9_SELECT_A::INPUT)
242    }
243    #[doc = "`10`"]
244    #[inline(always)]
245    pub fn uart1_cts(self) -> &'a mut crate::W<REG> {
246        self.variant(PG9_SELECT_A::UART1_CTS)
247    }
248    #[doc = "`100`"]
249    #[inline(always)]
250    pub fn rgmii_rxd3(self) -> &'a mut crate::W<REG> {
251        self.variant(PG9_SELECT_A::RGMII_RXD3)
252    }
253    #[doc = "`1110`"]
254    #[inline(always)]
255    pub fn pg_eint9(self) -> &'a mut crate::W<REG> {
256        self.variant(PG9_SELECT_A::PG_EINT9)
257    }
258    #[doc = "`1`"]
259    #[inline(always)]
260    pub fn output(self) -> &'a mut crate::W<REG> {
261        self.variant(PG9_SELECT_A::OUTPUT)
262    }
263    #[doc = "`11`"]
264    #[inline(always)]
265    pub fn twi1_sda(self) -> &'a mut crate::W<REG> {
266        self.variant(PG9_SELECT_A::TWI1_SDA)
267    }
268    #[doc = "`101`"]
269    #[inline(always)]
270    pub fn uart3_rx(self) -> &'a mut crate::W<REG> {
271        self.variant(PG9_SELECT_A::UART3_RX)
272    }
273    #[doc = "`1111`"]
274    #[inline(always)]
275    pub fn io_disable(self) -> &'a mut crate::W<REG> {
276        self.variant(PG9_SELECT_A::IO_DISABLE)
277    }
278}
279#[doc = "Field `pg10_select` reader - PG10 Select"]
280pub type PG10_SELECT_R = crate::FieldReader<PG10_SELECT_A>;
281#[doc = "PG10 Select\n\nValue on reset: 0"]
282#[derive(Clone, Copy, Debug, PartialEq, Eq)]
283#[repr(u8)]
284pub enum PG10_SELECT_A {
285    #[doc = "0: `0`"]
286    INPUT = 0,
287    #[doc = "2: `10`"]
288    PWM3 = 2,
289    #[doc = "4: `100`"]
290    RGMII_RXCK = 4,
291    #[doc = "6: `110`"]
292    IR_RX = 6,
293    #[doc = "14: `1110`"]
294    PG_EINT10 = 14,
295    #[doc = "1: `1`"]
296    OUTPUT = 1,
297    #[doc = "3: `11`"]
298    TWI3_SCK = 3,
299    #[doc = "5: `101`"]
300    CLK_FANOUT0 = 5,
301    #[doc = "15: `1111`"]
302    IO_DISABLE = 15,
303}
304impl From<PG10_SELECT_A> for u8 {
305    #[inline(always)]
306    fn from(variant: PG10_SELECT_A) -> Self {
307        variant as _
308    }
309}
310impl crate::FieldSpec for PG10_SELECT_A {
311    type Ux = u8;
312}
313impl PG10_SELECT_R {
314    #[doc = "Get enumerated values variant"]
315    #[inline(always)]
316    pub const fn variant(&self) -> Option<PG10_SELECT_A> {
317        match self.bits {
318            0 => Some(PG10_SELECT_A::INPUT),
319            2 => Some(PG10_SELECT_A::PWM3),
320            4 => Some(PG10_SELECT_A::RGMII_RXCK),
321            6 => Some(PG10_SELECT_A::IR_RX),
322            14 => Some(PG10_SELECT_A::PG_EINT10),
323            1 => Some(PG10_SELECT_A::OUTPUT),
324            3 => Some(PG10_SELECT_A::TWI3_SCK),
325            5 => Some(PG10_SELECT_A::CLK_FANOUT0),
326            15 => Some(PG10_SELECT_A::IO_DISABLE),
327            _ => None,
328        }
329    }
330    #[doc = "`0`"]
331    #[inline(always)]
332    pub fn is_input(&self) -> bool {
333        *self == PG10_SELECT_A::INPUT
334    }
335    #[doc = "`10`"]
336    #[inline(always)]
337    pub fn is_pwm3(&self) -> bool {
338        *self == PG10_SELECT_A::PWM3
339    }
340    #[doc = "`100`"]
341    #[inline(always)]
342    pub fn is_rgmii_rxck(&self) -> bool {
343        *self == PG10_SELECT_A::RGMII_RXCK
344    }
345    #[doc = "`110`"]
346    #[inline(always)]
347    pub fn is_ir_rx(&self) -> bool {
348        *self == PG10_SELECT_A::IR_RX
349    }
350    #[doc = "`1110`"]
351    #[inline(always)]
352    pub fn is_pg_eint10(&self) -> bool {
353        *self == PG10_SELECT_A::PG_EINT10
354    }
355    #[doc = "`1`"]
356    #[inline(always)]
357    pub fn is_output(&self) -> bool {
358        *self == PG10_SELECT_A::OUTPUT
359    }
360    #[doc = "`11`"]
361    #[inline(always)]
362    pub fn is_twi3_sck(&self) -> bool {
363        *self == PG10_SELECT_A::TWI3_SCK
364    }
365    #[doc = "`101`"]
366    #[inline(always)]
367    pub fn is_clk_fanout0(&self) -> bool {
368        *self == PG10_SELECT_A::CLK_FANOUT0
369    }
370    #[doc = "`1111`"]
371    #[inline(always)]
372    pub fn is_io_disable(&self) -> bool {
373        *self == PG10_SELECT_A::IO_DISABLE
374    }
375}
376#[doc = "Field `pg10_select` writer - PG10 Select"]
377pub type PG10_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG10_SELECT_A>;
378impl<'a, REG> PG10_SELECT_W<'a, REG>
379where
380    REG: crate::Writable + crate::RegisterSpec,
381    REG::Ux: From<u8>,
382{
383    #[doc = "`0`"]
384    #[inline(always)]
385    pub fn input(self) -> &'a mut crate::W<REG> {
386        self.variant(PG10_SELECT_A::INPUT)
387    }
388    #[doc = "`10`"]
389    #[inline(always)]
390    pub fn pwm3(self) -> &'a mut crate::W<REG> {
391        self.variant(PG10_SELECT_A::PWM3)
392    }
393    #[doc = "`100`"]
394    #[inline(always)]
395    pub fn rgmii_rxck(self) -> &'a mut crate::W<REG> {
396        self.variant(PG10_SELECT_A::RGMII_RXCK)
397    }
398    #[doc = "`110`"]
399    #[inline(always)]
400    pub fn ir_rx(self) -> &'a mut crate::W<REG> {
401        self.variant(PG10_SELECT_A::IR_RX)
402    }
403    #[doc = "`1110`"]
404    #[inline(always)]
405    pub fn pg_eint10(self) -> &'a mut crate::W<REG> {
406        self.variant(PG10_SELECT_A::PG_EINT10)
407    }
408    #[doc = "`1`"]
409    #[inline(always)]
410    pub fn output(self) -> &'a mut crate::W<REG> {
411        self.variant(PG10_SELECT_A::OUTPUT)
412    }
413    #[doc = "`11`"]
414    #[inline(always)]
415    pub fn twi3_sck(self) -> &'a mut crate::W<REG> {
416        self.variant(PG10_SELECT_A::TWI3_SCK)
417    }
418    #[doc = "`101`"]
419    #[inline(always)]
420    pub fn clk_fanout0(self) -> &'a mut crate::W<REG> {
421        self.variant(PG10_SELECT_A::CLK_FANOUT0)
422    }
423    #[doc = "`1111`"]
424    #[inline(always)]
425    pub fn io_disable(self) -> &'a mut crate::W<REG> {
426        self.variant(PG10_SELECT_A::IO_DISABLE)
427    }
428}
429#[doc = "Field `pg11_select` reader - PG11 Select"]
430pub type PG11_SELECT_R = crate::FieldReader<PG11_SELECT_A>;
431#[doc = "PG11 Select\n\nValue on reset: 0"]
432#[derive(Clone, Copy, Debug, PartialEq, Eq)]
433#[repr(u8)]
434pub enum PG11_SELECT_A {
435    #[doc = "0: `0`"]
436    INPUT = 0,
437    #[doc = "2: `10`"]
438    I2S1_MCLK = 2,
439    #[doc = "4: `100`"]
440    EPHY_25M = 4,
441    #[doc = "6: `110`"]
442    TCON_TRIG = 6,
443    #[doc = "14: `1110`"]
444    PG_EINT11 = 14,
445    #[doc = "1: `1`"]
446    OUTPUT = 1,
447    #[doc = "3: `11`"]
448    TWI3_SDA = 3,
449    #[doc = "5: `101`"]
450    CLK_FANOUT1 = 5,
451    #[doc = "15: `1111`"]
452    IO_DISABLE = 15,
453}
454impl From<PG11_SELECT_A> for u8 {
455    #[inline(always)]
456    fn from(variant: PG11_SELECT_A) -> Self {
457        variant as _
458    }
459}
460impl crate::FieldSpec for PG11_SELECT_A {
461    type Ux = u8;
462}
463impl PG11_SELECT_R {
464    #[doc = "Get enumerated values variant"]
465    #[inline(always)]
466    pub const fn variant(&self) -> Option<PG11_SELECT_A> {
467        match self.bits {
468            0 => Some(PG11_SELECT_A::INPUT),
469            2 => Some(PG11_SELECT_A::I2S1_MCLK),
470            4 => Some(PG11_SELECT_A::EPHY_25M),
471            6 => Some(PG11_SELECT_A::TCON_TRIG),
472            14 => Some(PG11_SELECT_A::PG_EINT11),
473            1 => Some(PG11_SELECT_A::OUTPUT),
474            3 => Some(PG11_SELECT_A::TWI3_SDA),
475            5 => Some(PG11_SELECT_A::CLK_FANOUT1),
476            15 => Some(PG11_SELECT_A::IO_DISABLE),
477            _ => None,
478        }
479    }
480    #[doc = "`0`"]
481    #[inline(always)]
482    pub fn is_input(&self) -> bool {
483        *self == PG11_SELECT_A::INPUT
484    }
485    #[doc = "`10`"]
486    #[inline(always)]
487    pub fn is_i2s1_mclk(&self) -> bool {
488        *self == PG11_SELECT_A::I2S1_MCLK
489    }
490    #[doc = "`100`"]
491    #[inline(always)]
492    pub fn is_ephy_25m(&self) -> bool {
493        *self == PG11_SELECT_A::EPHY_25M
494    }
495    #[doc = "`110`"]
496    #[inline(always)]
497    pub fn is_tcon_trig(&self) -> bool {
498        *self == PG11_SELECT_A::TCON_TRIG
499    }
500    #[doc = "`1110`"]
501    #[inline(always)]
502    pub fn is_pg_eint11(&self) -> bool {
503        *self == PG11_SELECT_A::PG_EINT11
504    }
505    #[doc = "`1`"]
506    #[inline(always)]
507    pub fn is_output(&self) -> bool {
508        *self == PG11_SELECT_A::OUTPUT
509    }
510    #[doc = "`11`"]
511    #[inline(always)]
512    pub fn is_twi3_sda(&self) -> bool {
513        *self == PG11_SELECT_A::TWI3_SDA
514    }
515    #[doc = "`101`"]
516    #[inline(always)]
517    pub fn is_clk_fanout1(&self) -> bool {
518        *self == PG11_SELECT_A::CLK_FANOUT1
519    }
520    #[doc = "`1111`"]
521    #[inline(always)]
522    pub fn is_io_disable(&self) -> bool {
523        *self == PG11_SELECT_A::IO_DISABLE
524    }
525}
526#[doc = "Field `pg11_select` writer - PG11 Select"]
527pub type PG11_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG11_SELECT_A>;
528impl<'a, REG> PG11_SELECT_W<'a, REG>
529where
530    REG: crate::Writable + crate::RegisterSpec,
531    REG::Ux: From<u8>,
532{
533    #[doc = "`0`"]
534    #[inline(always)]
535    pub fn input(self) -> &'a mut crate::W<REG> {
536        self.variant(PG11_SELECT_A::INPUT)
537    }
538    #[doc = "`10`"]
539    #[inline(always)]
540    pub fn i2s1_mclk(self) -> &'a mut crate::W<REG> {
541        self.variant(PG11_SELECT_A::I2S1_MCLK)
542    }
543    #[doc = "`100`"]
544    #[inline(always)]
545    pub fn ephy_25m(self) -> &'a mut crate::W<REG> {
546        self.variant(PG11_SELECT_A::EPHY_25M)
547    }
548    #[doc = "`110`"]
549    #[inline(always)]
550    pub fn tcon_trig(self) -> &'a mut crate::W<REG> {
551        self.variant(PG11_SELECT_A::TCON_TRIG)
552    }
553    #[doc = "`1110`"]
554    #[inline(always)]
555    pub fn pg_eint11(self) -> &'a mut crate::W<REG> {
556        self.variant(PG11_SELECT_A::PG_EINT11)
557    }
558    #[doc = "`1`"]
559    #[inline(always)]
560    pub fn output(self) -> &'a mut crate::W<REG> {
561        self.variant(PG11_SELECT_A::OUTPUT)
562    }
563    #[doc = "`11`"]
564    #[inline(always)]
565    pub fn twi3_sda(self) -> &'a mut crate::W<REG> {
566        self.variant(PG11_SELECT_A::TWI3_SDA)
567    }
568    #[doc = "`101`"]
569    #[inline(always)]
570    pub fn clk_fanout1(self) -> &'a mut crate::W<REG> {
571        self.variant(PG11_SELECT_A::CLK_FANOUT1)
572    }
573    #[doc = "`1111`"]
574    #[inline(always)]
575    pub fn io_disable(self) -> &'a mut crate::W<REG> {
576        self.variant(PG11_SELECT_A::IO_DISABLE)
577    }
578}
579#[doc = "Field `pg12_select` reader - PG12 Select"]
580pub type PG12_SELECT_R = crate::FieldReader<PG12_SELECT_A>;
581#[doc = "PG12 Select\n\nValue on reset: 0"]
582#[derive(Clone, Copy, Debug, PartialEq, Eq)]
583#[repr(u8)]
584pub enum PG12_SELECT_A {
585    #[doc = "0: `0`"]
586    INPUT = 0,
587    #[doc = "1: `1`"]
588    OUTPUT = 1,
589    #[doc = "2: `10`"]
590    I2S1_LRCK = 2,
591    #[doc = "3: `11`"]
592    TWI0_SCK = 3,
593    #[doc = "4: `100`"]
594    RGMII_TXCTRL_RMII_TXEN = 4,
595    #[doc = "5: `101`"]
596    CLK_FANOUT2 = 5,
597    #[doc = "6: `110`"]
598    PWM0 = 6,
599    #[doc = "14: `1110`"]
600    PG_EINT12 = 14,
601    #[doc = "7: `111`"]
602    UART1_TX = 7,
603    #[doc = "15: `1111`"]
604    IO_DISABLE = 15,
605}
606impl From<PG12_SELECT_A> for u8 {
607    #[inline(always)]
608    fn from(variant: PG12_SELECT_A) -> Self {
609        variant as _
610    }
611}
612impl crate::FieldSpec for PG12_SELECT_A {
613    type Ux = u8;
614}
615impl PG12_SELECT_R {
616    #[doc = "Get enumerated values variant"]
617    #[inline(always)]
618    pub const fn variant(&self) -> Option<PG12_SELECT_A> {
619        match self.bits {
620            0 => Some(PG12_SELECT_A::INPUT),
621            1 => Some(PG12_SELECT_A::OUTPUT),
622            2 => Some(PG12_SELECT_A::I2S1_LRCK),
623            3 => Some(PG12_SELECT_A::TWI0_SCK),
624            4 => Some(PG12_SELECT_A::RGMII_TXCTRL_RMII_TXEN),
625            5 => Some(PG12_SELECT_A::CLK_FANOUT2),
626            6 => Some(PG12_SELECT_A::PWM0),
627            14 => Some(PG12_SELECT_A::PG_EINT12),
628            7 => Some(PG12_SELECT_A::UART1_TX),
629            15 => Some(PG12_SELECT_A::IO_DISABLE),
630            _ => None,
631        }
632    }
633    #[doc = "`0`"]
634    #[inline(always)]
635    pub fn is_input(&self) -> bool {
636        *self == PG12_SELECT_A::INPUT
637    }
638    #[doc = "`1`"]
639    #[inline(always)]
640    pub fn is_output(&self) -> bool {
641        *self == PG12_SELECT_A::OUTPUT
642    }
643    #[doc = "`10`"]
644    #[inline(always)]
645    pub fn is_i2s1_lrck(&self) -> bool {
646        *self == PG12_SELECT_A::I2S1_LRCK
647    }
648    #[doc = "`11`"]
649    #[inline(always)]
650    pub fn is_twi0_sck(&self) -> bool {
651        *self == PG12_SELECT_A::TWI0_SCK
652    }
653    #[doc = "`100`"]
654    #[inline(always)]
655    pub fn is_rgmii_txctrl_rmii_txen(&self) -> bool {
656        *self == PG12_SELECT_A::RGMII_TXCTRL_RMII_TXEN
657    }
658    #[doc = "`101`"]
659    #[inline(always)]
660    pub fn is_clk_fanout2(&self) -> bool {
661        *self == PG12_SELECT_A::CLK_FANOUT2
662    }
663    #[doc = "`110`"]
664    #[inline(always)]
665    pub fn is_pwm0(&self) -> bool {
666        *self == PG12_SELECT_A::PWM0
667    }
668    #[doc = "`1110`"]
669    #[inline(always)]
670    pub fn is_pg_eint12(&self) -> bool {
671        *self == PG12_SELECT_A::PG_EINT12
672    }
673    #[doc = "`111`"]
674    #[inline(always)]
675    pub fn is_uart1_tx(&self) -> bool {
676        *self == PG12_SELECT_A::UART1_TX
677    }
678    #[doc = "`1111`"]
679    #[inline(always)]
680    pub fn is_io_disable(&self) -> bool {
681        *self == PG12_SELECT_A::IO_DISABLE
682    }
683}
684#[doc = "Field `pg12_select` writer - PG12 Select"]
685pub type PG12_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG12_SELECT_A>;
686impl<'a, REG> PG12_SELECT_W<'a, REG>
687where
688    REG: crate::Writable + crate::RegisterSpec,
689    REG::Ux: From<u8>,
690{
691    #[doc = "`0`"]
692    #[inline(always)]
693    pub fn input(self) -> &'a mut crate::W<REG> {
694        self.variant(PG12_SELECT_A::INPUT)
695    }
696    #[doc = "`1`"]
697    #[inline(always)]
698    pub fn output(self) -> &'a mut crate::W<REG> {
699        self.variant(PG12_SELECT_A::OUTPUT)
700    }
701    #[doc = "`10`"]
702    #[inline(always)]
703    pub fn i2s1_lrck(self) -> &'a mut crate::W<REG> {
704        self.variant(PG12_SELECT_A::I2S1_LRCK)
705    }
706    #[doc = "`11`"]
707    #[inline(always)]
708    pub fn twi0_sck(self) -> &'a mut crate::W<REG> {
709        self.variant(PG12_SELECT_A::TWI0_SCK)
710    }
711    #[doc = "`100`"]
712    #[inline(always)]
713    pub fn rgmii_txctrl_rmii_txen(self) -> &'a mut crate::W<REG> {
714        self.variant(PG12_SELECT_A::RGMII_TXCTRL_RMII_TXEN)
715    }
716    #[doc = "`101`"]
717    #[inline(always)]
718    pub fn clk_fanout2(self) -> &'a mut crate::W<REG> {
719        self.variant(PG12_SELECT_A::CLK_FANOUT2)
720    }
721    #[doc = "`110`"]
722    #[inline(always)]
723    pub fn pwm0(self) -> &'a mut crate::W<REG> {
724        self.variant(PG12_SELECT_A::PWM0)
725    }
726    #[doc = "`1110`"]
727    #[inline(always)]
728    pub fn pg_eint12(self) -> &'a mut crate::W<REG> {
729        self.variant(PG12_SELECT_A::PG_EINT12)
730    }
731    #[doc = "`111`"]
732    #[inline(always)]
733    pub fn uart1_tx(self) -> &'a mut crate::W<REG> {
734        self.variant(PG12_SELECT_A::UART1_TX)
735    }
736    #[doc = "`1111`"]
737    #[inline(always)]
738    pub fn io_disable(self) -> &'a mut crate::W<REG> {
739        self.variant(PG12_SELECT_A::IO_DISABLE)
740    }
741}
742#[doc = "Field `pg13_select` reader - PG13 Select"]
743pub type PG13_SELECT_R = crate::FieldReader<PG13_SELECT_A>;
744#[doc = "PG13 Select\n\nValue on reset: 0"]
745#[derive(Clone, Copy, Debug, PartialEq, Eq)]
746#[repr(u8)]
747pub enum PG13_SELECT_A {
748    #[doc = "0: `0`"]
749    INPUT = 0,
750    #[doc = "2: `10`"]
751    I2S1_BCLK = 2,
752    #[doc = "4: `100`"]
753    RGMII_CLKIN_RMII_RXER = 4,
754    #[doc = "6: `110`"]
755    LEDC_DO = 6,
756    #[doc = "14: `1110`"]
757    PG_EINT13 = 14,
758    #[doc = "1: `1`"]
759    OUTPUT = 1,
760    #[doc = "3: `11`"]
761    TWI0_SDA = 3,
762    #[doc = "5: `101`"]
763    PWM2 = 5,
764    #[doc = "7: `111`"]
765    UART1_RX = 7,
766    #[doc = "15: `1111`"]
767    IO_DISABLE = 15,
768}
769impl From<PG13_SELECT_A> for u8 {
770    #[inline(always)]
771    fn from(variant: PG13_SELECT_A) -> Self {
772        variant as _
773    }
774}
775impl crate::FieldSpec for PG13_SELECT_A {
776    type Ux = u8;
777}
778impl PG13_SELECT_R {
779    #[doc = "Get enumerated values variant"]
780    #[inline(always)]
781    pub const fn variant(&self) -> Option<PG13_SELECT_A> {
782        match self.bits {
783            0 => Some(PG13_SELECT_A::INPUT),
784            2 => Some(PG13_SELECT_A::I2S1_BCLK),
785            4 => Some(PG13_SELECT_A::RGMII_CLKIN_RMII_RXER),
786            6 => Some(PG13_SELECT_A::LEDC_DO),
787            14 => Some(PG13_SELECT_A::PG_EINT13),
788            1 => Some(PG13_SELECT_A::OUTPUT),
789            3 => Some(PG13_SELECT_A::TWI0_SDA),
790            5 => Some(PG13_SELECT_A::PWM2),
791            7 => Some(PG13_SELECT_A::UART1_RX),
792            15 => Some(PG13_SELECT_A::IO_DISABLE),
793            _ => None,
794        }
795    }
796    #[doc = "`0`"]
797    #[inline(always)]
798    pub fn is_input(&self) -> bool {
799        *self == PG13_SELECT_A::INPUT
800    }
801    #[doc = "`10`"]
802    #[inline(always)]
803    pub fn is_i2s1_bclk(&self) -> bool {
804        *self == PG13_SELECT_A::I2S1_BCLK
805    }
806    #[doc = "`100`"]
807    #[inline(always)]
808    pub fn is_rgmii_clkin_rmii_rxer(&self) -> bool {
809        *self == PG13_SELECT_A::RGMII_CLKIN_RMII_RXER
810    }
811    #[doc = "`110`"]
812    #[inline(always)]
813    pub fn is_ledc_do(&self) -> bool {
814        *self == PG13_SELECT_A::LEDC_DO
815    }
816    #[doc = "`1110`"]
817    #[inline(always)]
818    pub fn is_pg_eint13(&self) -> bool {
819        *self == PG13_SELECT_A::PG_EINT13
820    }
821    #[doc = "`1`"]
822    #[inline(always)]
823    pub fn is_output(&self) -> bool {
824        *self == PG13_SELECT_A::OUTPUT
825    }
826    #[doc = "`11`"]
827    #[inline(always)]
828    pub fn is_twi0_sda(&self) -> bool {
829        *self == PG13_SELECT_A::TWI0_SDA
830    }
831    #[doc = "`101`"]
832    #[inline(always)]
833    pub fn is_pwm2(&self) -> bool {
834        *self == PG13_SELECT_A::PWM2
835    }
836    #[doc = "`111`"]
837    #[inline(always)]
838    pub fn is_uart1_rx(&self) -> bool {
839        *self == PG13_SELECT_A::UART1_RX
840    }
841    #[doc = "`1111`"]
842    #[inline(always)]
843    pub fn is_io_disable(&self) -> bool {
844        *self == PG13_SELECT_A::IO_DISABLE
845    }
846}
847#[doc = "Field `pg13_select` writer - PG13 Select"]
848pub type PG13_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG13_SELECT_A>;
849impl<'a, REG> PG13_SELECT_W<'a, REG>
850where
851    REG: crate::Writable + crate::RegisterSpec,
852    REG::Ux: From<u8>,
853{
854    #[doc = "`0`"]
855    #[inline(always)]
856    pub fn input(self) -> &'a mut crate::W<REG> {
857        self.variant(PG13_SELECT_A::INPUT)
858    }
859    #[doc = "`10`"]
860    #[inline(always)]
861    pub fn i2s1_bclk(self) -> &'a mut crate::W<REG> {
862        self.variant(PG13_SELECT_A::I2S1_BCLK)
863    }
864    #[doc = "`100`"]
865    #[inline(always)]
866    pub fn rgmii_clkin_rmii_rxer(self) -> &'a mut crate::W<REG> {
867        self.variant(PG13_SELECT_A::RGMII_CLKIN_RMII_RXER)
868    }
869    #[doc = "`110`"]
870    #[inline(always)]
871    pub fn ledc_do(self) -> &'a mut crate::W<REG> {
872        self.variant(PG13_SELECT_A::LEDC_DO)
873    }
874    #[doc = "`1110`"]
875    #[inline(always)]
876    pub fn pg_eint13(self) -> &'a mut crate::W<REG> {
877        self.variant(PG13_SELECT_A::PG_EINT13)
878    }
879    #[doc = "`1`"]
880    #[inline(always)]
881    pub fn output(self) -> &'a mut crate::W<REG> {
882        self.variant(PG13_SELECT_A::OUTPUT)
883    }
884    #[doc = "`11`"]
885    #[inline(always)]
886    pub fn twi0_sda(self) -> &'a mut crate::W<REG> {
887        self.variant(PG13_SELECT_A::TWI0_SDA)
888    }
889    #[doc = "`101`"]
890    #[inline(always)]
891    pub fn pwm2(self) -> &'a mut crate::W<REG> {
892        self.variant(PG13_SELECT_A::PWM2)
893    }
894    #[doc = "`111`"]
895    #[inline(always)]
896    pub fn uart1_rx(self) -> &'a mut crate::W<REG> {
897        self.variant(PG13_SELECT_A::UART1_RX)
898    }
899    #[doc = "`1111`"]
900    #[inline(always)]
901    pub fn io_disable(self) -> &'a mut crate::W<REG> {
902        self.variant(PG13_SELECT_A::IO_DISABLE)
903    }
904}
905#[doc = "Field `pg14_select` reader - PG14 Select"]
906pub type PG14_SELECT_R = crate::FieldReader<PG14_SELECT_A>;
907#[doc = "PG14 Select\n\nValue on reset: 0"]
908#[derive(Clone, Copy, Debug, PartialEq, Eq)]
909#[repr(u8)]
910pub enum PG14_SELECT_A {
911    #[doc = "0: `0`"]
912    INPUT = 0,
913    #[doc = "2: `10`"]
914    I2S1_DIN0 = 2,
915    #[doc = "4: `100`"]
916    MDC = 4,
917    #[doc = "6: `110`"]
918    SPI0_WP = 6,
919    #[doc = "14: `1110`"]
920    PG_EINT14 = 14,
921    #[doc = "1: `1`"]
922    OUTPUT = 1,
923    #[doc = "3: `11`"]
924    TWI2_SCK = 3,
925    #[doc = "5: `101`"]
926    I2S1_DOUT1 = 5,
927    #[doc = "7: `111`"]
928    UART1_RTS = 7,
929    #[doc = "15: `1111`"]
930    IO_DISABLE = 15,
931}
932impl From<PG14_SELECT_A> for u8 {
933    #[inline(always)]
934    fn from(variant: PG14_SELECT_A) -> Self {
935        variant as _
936    }
937}
938impl crate::FieldSpec for PG14_SELECT_A {
939    type Ux = u8;
940}
941impl PG14_SELECT_R {
942    #[doc = "Get enumerated values variant"]
943    #[inline(always)]
944    pub const fn variant(&self) -> Option<PG14_SELECT_A> {
945        match self.bits {
946            0 => Some(PG14_SELECT_A::INPUT),
947            2 => Some(PG14_SELECT_A::I2S1_DIN0),
948            4 => Some(PG14_SELECT_A::MDC),
949            6 => Some(PG14_SELECT_A::SPI0_WP),
950            14 => Some(PG14_SELECT_A::PG_EINT14),
951            1 => Some(PG14_SELECT_A::OUTPUT),
952            3 => Some(PG14_SELECT_A::TWI2_SCK),
953            5 => Some(PG14_SELECT_A::I2S1_DOUT1),
954            7 => Some(PG14_SELECT_A::UART1_RTS),
955            15 => Some(PG14_SELECT_A::IO_DISABLE),
956            _ => None,
957        }
958    }
959    #[doc = "`0`"]
960    #[inline(always)]
961    pub fn is_input(&self) -> bool {
962        *self == PG14_SELECT_A::INPUT
963    }
964    #[doc = "`10`"]
965    #[inline(always)]
966    pub fn is_i2s1_din0(&self) -> bool {
967        *self == PG14_SELECT_A::I2S1_DIN0
968    }
969    #[doc = "`100`"]
970    #[inline(always)]
971    pub fn is_mdc(&self) -> bool {
972        *self == PG14_SELECT_A::MDC
973    }
974    #[doc = "`110`"]
975    #[inline(always)]
976    pub fn is_spi0_wp(&self) -> bool {
977        *self == PG14_SELECT_A::SPI0_WP
978    }
979    #[doc = "`1110`"]
980    #[inline(always)]
981    pub fn is_pg_eint14(&self) -> bool {
982        *self == PG14_SELECT_A::PG_EINT14
983    }
984    #[doc = "`1`"]
985    #[inline(always)]
986    pub fn is_output(&self) -> bool {
987        *self == PG14_SELECT_A::OUTPUT
988    }
989    #[doc = "`11`"]
990    #[inline(always)]
991    pub fn is_twi2_sck(&self) -> bool {
992        *self == PG14_SELECT_A::TWI2_SCK
993    }
994    #[doc = "`101`"]
995    #[inline(always)]
996    pub fn is_i2s1_dout1(&self) -> bool {
997        *self == PG14_SELECT_A::I2S1_DOUT1
998    }
999    #[doc = "`111`"]
1000    #[inline(always)]
1001    pub fn is_uart1_rts(&self) -> bool {
1002        *self == PG14_SELECT_A::UART1_RTS
1003    }
1004    #[doc = "`1111`"]
1005    #[inline(always)]
1006    pub fn is_io_disable(&self) -> bool {
1007        *self == PG14_SELECT_A::IO_DISABLE
1008    }
1009}
1010#[doc = "Field `pg14_select` writer - PG14 Select"]
1011pub type PG14_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG14_SELECT_A>;
1012impl<'a, REG> PG14_SELECT_W<'a, REG>
1013where
1014    REG: crate::Writable + crate::RegisterSpec,
1015    REG::Ux: From<u8>,
1016{
1017    #[doc = "`0`"]
1018    #[inline(always)]
1019    pub fn input(self) -> &'a mut crate::W<REG> {
1020        self.variant(PG14_SELECT_A::INPUT)
1021    }
1022    #[doc = "`10`"]
1023    #[inline(always)]
1024    pub fn i2s1_din0(self) -> &'a mut crate::W<REG> {
1025        self.variant(PG14_SELECT_A::I2S1_DIN0)
1026    }
1027    #[doc = "`100`"]
1028    #[inline(always)]
1029    pub fn mdc(self) -> &'a mut crate::W<REG> {
1030        self.variant(PG14_SELECT_A::MDC)
1031    }
1032    #[doc = "`110`"]
1033    #[inline(always)]
1034    pub fn spi0_wp(self) -> &'a mut crate::W<REG> {
1035        self.variant(PG14_SELECT_A::SPI0_WP)
1036    }
1037    #[doc = "`1110`"]
1038    #[inline(always)]
1039    pub fn pg_eint14(self) -> &'a mut crate::W<REG> {
1040        self.variant(PG14_SELECT_A::PG_EINT14)
1041    }
1042    #[doc = "`1`"]
1043    #[inline(always)]
1044    pub fn output(self) -> &'a mut crate::W<REG> {
1045        self.variant(PG14_SELECT_A::OUTPUT)
1046    }
1047    #[doc = "`11`"]
1048    #[inline(always)]
1049    pub fn twi2_sck(self) -> &'a mut crate::W<REG> {
1050        self.variant(PG14_SELECT_A::TWI2_SCK)
1051    }
1052    #[doc = "`101`"]
1053    #[inline(always)]
1054    pub fn i2s1_dout1(self) -> &'a mut crate::W<REG> {
1055        self.variant(PG14_SELECT_A::I2S1_DOUT1)
1056    }
1057    #[doc = "`111`"]
1058    #[inline(always)]
1059    pub fn uart1_rts(self) -> &'a mut crate::W<REG> {
1060        self.variant(PG14_SELECT_A::UART1_RTS)
1061    }
1062    #[doc = "`1111`"]
1063    #[inline(always)]
1064    pub fn io_disable(self) -> &'a mut crate::W<REG> {
1065        self.variant(PG14_SELECT_A::IO_DISABLE)
1066    }
1067}
1068#[doc = "Field `pg15_select` reader - PG15 Select"]
1069pub type PG15_SELECT_R = crate::FieldReader<PG15_SELECT_A>;
1070#[doc = "PG15 Select\n\nValue on reset: 0"]
1071#[derive(Clone, Copy, Debug, PartialEq, Eq)]
1072#[repr(u8)]
1073pub enum PG15_SELECT_A {
1074    #[doc = "0: `0`"]
1075    INPUT = 0,
1076    #[doc = "2: `10`"]
1077    I2S1_DOUT0 = 2,
1078    #[doc = "4: `100`"]
1079    MDIO = 4,
1080    #[doc = "6: `110`"]
1081    SPI0_HOLD = 6,
1082    #[doc = "14: `1110`"]
1083    PG_EINT15 = 14,
1084    #[doc = "1: `1`"]
1085    OUTPUT = 1,
1086    #[doc = "3: `11`"]
1087    TWI2_SDA = 3,
1088    #[doc = "5: `101`"]
1089    I2S1_DIN1 = 5,
1090    #[doc = "7: `111`"]
1091    UART1_CTS = 7,
1092    #[doc = "15: `1111`"]
1093    IO_DISABLE = 15,
1094}
1095impl From<PG15_SELECT_A> for u8 {
1096    #[inline(always)]
1097    fn from(variant: PG15_SELECT_A) -> Self {
1098        variant as _
1099    }
1100}
1101impl crate::FieldSpec for PG15_SELECT_A {
1102    type Ux = u8;
1103}
1104impl PG15_SELECT_R {
1105    #[doc = "Get enumerated values variant"]
1106    #[inline(always)]
1107    pub const fn variant(&self) -> Option<PG15_SELECT_A> {
1108        match self.bits {
1109            0 => Some(PG15_SELECT_A::INPUT),
1110            2 => Some(PG15_SELECT_A::I2S1_DOUT0),
1111            4 => Some(PG15_SELECT_A::MDIO),
1112            6 => Some(PG15_SELECT_A::SPI0_HOLD),
1113            14 => Some(PG15_SELECT_A::PG_EINT15),
1114            1 => Some(PG15_SELECT_A::OUTPUT),
1115            3 => Some(PG15_SELECT_A::TWI2_SDA),
1116            5 => Some(PG15_SELECT_A::I2S1_DIN1),
1117            7 => Some(PG15_SELECT_A::UART1_CTS),
1118            15 => Some(PG15_SELECT_A::IO_DISABLE),
1119            _ => None,
1120        }
1121    }
1122    #[doc = "`0`"]
1123    #[inline(always)]
1124    pub fn is_input(&self) -> bool {
1125        *self == PG15_SELECT_A::INPUT
1126    }
1127    #[doc = "`10`"]
1128    #[inline(always)]
1129    pub fn is_i2s1_dout0(&self) -> bool {
1130        *self == PG15_SELECT_A::I2S1_DOUT0
1131    }
1132    #[doc = "`100`"]
1133    #[inline(always)]
1134    pub fn is_mdio(&self) -> bool {
1135        *self == PG15_SELECT_A::MDIO
1136    }
1137    #[doc = "`110`"]
1138    #[inline(always)]
1139    pub fn is_spi0_hold(&self) -> bool {
1140        *self == PG15_SELECT_A::SPI0_HOLD
1141    }
1142    #[doc = "`1110`"]
1143    #[inline(always)]
1144    pub fn is_pg_eint15(&self) -> bool {
1145        *self == PG15_SELECT_A::PG_EINT15
1146    }
1147    #[doc = "`1`"]
1148    #[inline(always)]
1149    pub fn is_output(&self) -> bool {
1150        *self == PG15_SELECT_A::OUTPUT
1151    }
1152    #[doc = "`11`"]
1153    #[inline(always)]
1154    pub fn is_twi2_sda(&self) -> bool {
1155        *self == PG15_SELECT_A::TWI2_SDA
1156    }
1157    #[doc = "`101`"]
1158    #[inline(always)]
1159    pub fn is_i2s1_din1(&self) -> bool {
1160        *self == PG15_SELECT_A::I2S1_DIN1
1161    }
1162    #[doc = "`111`"]
1163    #[inline(always)]
1164    pub fn is_uart1_cts(&self) -> bool {
1165        *self == PG15_SELECT_A::UART1_CTS
1166    }
1167    #[doc = "`1111`"]
1168    #[inline(always)]
1169    pub fn is_io_disable(&self) -> bool {
1170        *self == PG15_SELECT_A::IO_DISABLE
1171    }
1172}
1173#[doc = "Field `pg15_select` writer - PG15 Select"]
1174pub type PG15_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG15_SELECT_A>;
1175impl<'a, REG> PG15_SELECT_W<'a, REG>
1176where
1177    REG: crate::Writable + crate::RegisterSpec,
1178    REG::Ux: From<u8>,
1179{
1180    #[doc = "`0`"]
1181    #[inline(always)]
1182    pub fn input(self) -> &'a mut crate::W<REG> {
1183        self.variant(PG15_SELECT_A::INPUT)
1184    }
1185    #[doc = "`10`"]
1186    #[inline(always)]
1187    pub fn i2s1_dout0(self) -> &'a mut crate::W<REG> {
1188        self.variant(PG15_SELECT_A::I2S1_DOUT0)
1189    }
1190    #[doc = "`100`"]
1191    #[inline(always)]
1192    pub fn mdio(self) -> &'a mut crate::W<REG> {
1193        self.variant(PG15_SELECT_A::MDIO)
1194    }
1195    #[doc = "`110`"]
1196    #[inline(always)]
1197    pub fn spi0_hold(self) -> &'a mut crate::W<REG> {
1198        self.variant(PG15_SELECT_A::SPI0_HOLD)
1199    }
1200    #[doc = "`1110`"]
1201    #[inline(always)]
1202    pub fn pg_eint15(self) -> &'a mut crate::W<REG> {
1203        self.variant(PG15_SELECT_A::PG_EINT15)
1204    }
1205    #[doc = "`1`"]
1206    #[inline(always)]
1207    pub fn output(self) -> &'a mut crate::W<REG> {
1208        self.variant(PG15_SELECT_A::OUTPUT)
1209    }
1210    #[doc = "`11`"]
1211    #[inline(always)]
1212    pub fn twi2_sda(self) -> &'a mut crate::W<REG> {
1213        self.variant(PG15_SELECT_A::TWI2_SDA)
1214    }
1215    #[doc = "`101`"]
1216    #[inline(always)]
1217    pub fn i2s1_din1(self) -> &'a mut crate::W<REG> {
1218        self.variant(PG15_SELECT_A::I2S1_DIN1)
1219    }
1220    #[doc = "`111`"]
1221    #[inline(always)]
1222    pub fn uart1_cts(self) -> &'a mut crate::W<REG> {
1223        self.variant(PG15_SELECT_A::UART1_CTS)
1224    }
1225    #[doc = "`1111`"]
1226    #[inline(always)]
1227    pub fn io_disable(self) -> &'a mut crate::W<REG> {
1228        self.variant(PG15_SELECT_A::IO_DISABLE)
1229    }
1230}
1231impl R {
1232    #[doc = "Bits 0:3 - PG8 Select"]
1233    #[inline(always)]
1234    pub fn pg8_select(&self) -> PG8_SELECT_R {
1235        PG8_SELECT_R::new((self.bits & 0x0f) as u8)
1236    }
1237    #[doc = "Bits 4:7 - PG9 Select"]
1238    #[inline(always)]
1239    pub fn pg9_select(&self) -> PG9_SELECT_R {
1240        PG9_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
1241    }
1242    #[doc = "Bits 8:11 - PG10 Select"]
1243    #[inline(always)]
1244    pub fn pg10_select(&self) -> PG10_SELECT_R {
1245        PG10_SELECT_R::new(((self.bits >> 8) & 0x0f) as u8)
1246    }
1247    #[doc = "Bits 12:15 - PG11 Select"]
1248    #[inline(always)]
1249    pub fn pg11_select(&self) -> PG11_SELECT_R {
1250        PG11_SELECT_R::new(((self.bits >> 12) & 0x0f) as u8)
1251    }
1252    #[doc = "Bits 16:19 - PG12 Select"]
1253    #[inline(always)]
1254    pub fn pg12_select(&self) -> PG12_SELECT_R {
1255        PG12_SELECT_R::new(((self.bits >> 16) & 0x0f) as u8)
1256    }
1257    #[doc = "Bits 20:23 - PG13 Select"]
1258    #[inline(always)]
1259    pub fn pg13_select(&self) -> PG13_SELECT_R {
1260        PG13_SELECT_R::new(((self.bits >> 20) & 0x0f) as u8)
1261    }
1262    #[doc = "Bits 24:27 - PG14 Select"]
1263    #[inline(always)]
1264    pub fn pg14_select(&self) -> PG14_SELECT_R {
1265        PG14_SELECT_R::new(((self.bits >> 24) & 0x0f) as u8)
1266    }
1267    #[doc = "Bits 28:31 - PG15 Select"]
1268    #[inline(always)]
1269    pub fn pg15_select(&self) -> PG15_SELECT_R {
1270        PG15_SELECT_R::new(((self.bits >> 28) & 0x0f) as u8)
1271    }
1272}
1273impl W {
1274    #[doc = "Bits 0:3 - PG8 Select"]
1275    #[inline(always)]
1276    #[must_use]
1277    pub fn pg8_select(&mut self) -> PG8_SELECT_W<PG_CFG1_SPEC> {
1278        PG8_SELECT_W::new(self, 0)
1279    }
1280    #[doc = "Bits 4:7 - PG9 Select"]
1281    #[inline(always)]
1282    #[must_use]
1283    pub fn pg9_select(&mut self) -> PG9_SELECT_W<PG_CFG1_SPEC> {
1284        PG9_SELECT_W::new(self, 4)
1285    }
1286    #[doc = "Bits 8:11 - PG10 Select"]
1287    #[inline(always)]
1288    #[must_use]
1289    pub fn pg10_select(&mut self) -> PG10_SELECT_W<PG_CFG1_SPEC> {
1290        PG10_SELECT_W::new(self, 8)
1291    }
1292    #[doc = "Bits 12:15 - PG11 Select"]
1293    #[inline(always)]
1294    #[must_use]
1295    pub fn pg11_select(&mut self) -> PG11_SELECT_W<PG_CFG1_SPEC> {
1296        PG11_SELECT_W::new(self, 12)
1297    }
1298    #[doc = "Bits 16:19 - PG12 Select"]
1299    #[inline(always)]
1300    #[must_use]
1301    pub fn pg12_select(&mut self) -> PG12_SELECT_W<PG_CFG1_SPEC> {
1302        PG12_SELECT_W::new(self, 16)
1303    }
1304    #[doc = "Bits 20:23 - PG13 Select"]
1305    #[inline(always)]
1306    #[must_use]
1307    pub fn pg13_select(&mut self) -> PG13_SELECT_W<PG_CFG1_SPEC> {
1308        PG13_SELECT_W::new(self, 20)
1309    }
1310    #[doc = "Bits 24:27 - PG14 Select"]
1311    #[inline(always)]
1312    #[must_use]
1313    pub fn pg14_select(&mut self) -> PG14_SELECT_W<PG_CFG1_SPEC> {
1314        PG14_SELECT_W::new(self, 24)
1315    }
1316    #[doc = "Bits 28:31 - PG15 Select"]
1317    #[inline(always)]
1318    #[must_use]
1319    pub fn pg15_select(&mut self) -> PG15_SELECT_W<PG_CFG1_SPEC> {
1320        PG15_SELECT_W::new(self, 28)
1321    }
1322    #[doc = r" Writes raw bits to the register."]
1323    #[doc = r""]
1324    #[doc = r" # Safety"]
1325    #[doc = r""]
1326    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1327    #[inline(always)]
1328    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1329        self.bits = bits;
1330        self
1331    }
1332}
1333#[doc = "PG Configure Register 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pg_cfg1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pg_cfg1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1334pub struct PG_CFG1_SPEC;
1335impl crate::RegisterSpec for PG_CFG1_SPEC {
1336    type Ux = u32;
1337}
1338#[doc = "`read()` method returns [`pg_cfg1::R`](R) reader structure"]
1339impl crate::Readable for PG_CFG1_SPEC {}
1340#[doc = "`write(|w| ..)` method takes [`pg_cfg1::W`](W) writer structure"]
1341impl crate::Writable for PG_CFG1_SPEC {
1342    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1343    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1344}
1345#[doc = "`reset()` method sets pg_cfg1 to value 0"]
1346impl crate::Resettable for PG_CFG1_SPEC {
1347    const RESET_VALUE: Self::Ux = 0;
1348}
d1_pac/gpio/pg_cfg1.rs

d1_pac/gpio/
pg_cfg1.rs
