d1_pac/gpio/
pg_cfg0.rs

1#[doc = "Register `pg_cfg0` reader"]
2pub type R = crate::R<PG_CFG0_SPEC>;
3#[doc = "Register `pg_cfg0` writer"]
4pub type W = crate::W<PG_CFG0_SPEC>;
5#[doc = "Field `pg0_select` reader - PG0 Select"]
6pub type PG0_SELECT_R = crate::FieldReader<PG0_SELECT_A>;
7#[doc = "PG0 Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9#[repr(u8)]
10pub enum PG0_SELECT_A {
11    #[doc = "0: `0`"]
12    INPUT = 0,
13    #[doc = "2: `10`"]
14    SDC1_CLK = 2,
15    #[doc = "4: `100`"]
16    RGMII_RXCTRL_RMII_CRS_DV = 4,
17    #[doc = "14: `1110`"]
18    PG_EINT0 = 14,
19    #[doc = "1: `1`"]
20    OUTPUT = 1,
21    #[doc = "3: `11`"]
22    UART3_TX = 3,
23    #[doc = "5: `101`"]
24    PWM7 = 5,
25    #[doc = "15: `1111`"]
26    IO_DISABLE = 15,
27}
28impl From<PG0_SELECT_A> for u8 {
29    #[inline(always)]
30    fn from(variant: PG0_SELECT_A) -> Self {
31        variant as _
32    }
33}
34impl crate::FieldSpec for PG0_SELECT_A {
35    type Ux = u8;
36}
37impl PG0_SELECT_R {
38    #[doc = "Get enumerated values variant"]
39    #[inline(always)]
40    pub const fn variant(&self) -> Option<PG0_SELECT_A> {
41        match self.bits {
42            0 => Some(PG0_SELECT_A::INPUT),
43            2 => Some(PG0_SELECT_A::SDC1_CLK),
44            4 => Some(PG0_SELECT_A::RGMII_RXCTRL_RMII_CRS_DV),
45            14 => Some(PG0_SELECT_A::PG_EINT0),
46            1 => Some(PG0_SELECT_A::OUTPUT),
47            3 => Some(PG0_SELECT_A::UART3_TX),
48            5 => Some(PG0_SELECT_A::PWM7),
49            15 => Some(PG0_SELECT_A::IO_DISABLE),
50            _ => None,
51        }
52    }
53    #[doc = "`0`"]
54    #[inline(always)]
55    pub fn is_input(&self) -> bool {
56        *self == PG0_SELECT_A::INPUT
57    }
58    #[doc = "`10`"]
59    #[inline(always)]
60    pub fn is_sdc1_clk(&self) -> bool {
61        *self == PG0_SELECT_A::SDC1_CLK
62    }
63    #[doc = "`100`"]
64    #[inline(always)]
65    pub fn is_rgmii_rxctrl_rmii_crs_dv(&self) -> bool {
66        *self == PG0_SELECT_A::RGMII_RXCTRL_RMII_CRS_DV
67    }
68    #[doc = "`1110`"]
69    #[inline(always)]
70    pub fn is_pg_eint0(&self) -> bool {
71        *self == PG0_SELECT_A::PG_EINT0
72    }
73    #[doc = "`1`"]
74    #[inline(always)]
75    pub fn is_output(&self) -> bool {
76        *self == PG0_SELECT_A::OUTPUT
77    }
78    #[doc = "`11`"]
79    #[inline(always)]
80    pub fn is_uart3_tx(&self) -> bool {
81        *self == PG0_SELECT_A::UART3_TX
82    }
83    #[doc = "`101`"]
84    #[inline(always)]
85    pub fn is_pwm7(&self) -> bool {
86        *self == PG0_SELECT_A::PWM7
87    }
88    #[doc = "`1111`"]
89    #[inline(always)]
90    pub fn is_io_disable(&self) -> bool {
91        *self == PG0_SELECT_A::IO_DISABLE
92    }
93}
94#[doc = "Field `pg0_select` writer - PG0 Select"]
95pub type PG0_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG0_SELECT_A>;
96impl<'a, REG> PG0_SELECT_W<'a, REG>
97where
98    REG: crate::Writable + crate::RegisterSpec,
99    REG::Ux: From<u8>,
100{
101    #[doc = "`0`"]
102    #[inline(always)]
103    pub fn input(self) -> &'a mut crate::W<REG> {
104        self.variant(PG0_SELECT_A::INPUT)
105    }
106    #[doc = "`10`"]
107    #[inline(always)]
108    pub fn sdc1_clk(self) -> &'a mut crate::W<REG> {
109        self.variant(PG0_SELECT_A::SDC1_CLK)
110    }
111    #[doc = "`100`"]
112    #[inline(always)]
113    pub fn rgmii_rxctrl_rmii_crs_dv(self) -> &'a mut crate::W<REG> {
114        self.variant(PG0_SELECT_A::RGMII_RXCTRL_RMII_CRS_DV)
115    }
116    #[doc = "`1110`"]
117    #[inline(always)]
118    pub fn pg_eint0(self) -> &'a mut crate::W<REG> {
119        self.variant(PG0_SELECT_A::PG_EINT0)
120    }
121    #[doc = "`1`"]
122    #[inline(always)]
123    pub fn output(self) -> &'a mut crate::W<REG> {
124        self.variant(PG0_SELECT_A::OUTPUT)
125    }
126    #[doc = "`11`"]
127    #[inline(always)]
128    pub fn uart3_tx(self) -> &'a mut crate::W<REG> {
129        self.variant(PG0_SELECT_A::UART3_TX)
130    }
131    #[doc = "`101`"]
132    #[inline(always)]
133    pub fn pwm7(self) -> &'a mut crate::W<REG> {
134        self.variant(PG0_SELECT_A::PWM7)
135    }
136    #[doc = "`1111`"]
137    #[inline(always)]
138    pub fn io_disable(self) -> &'a mut crate::W<REG> {
139        self.variant(PG0_SELECT_A::IO_DISABLE)
140    }
141}
142#[doc = "Field `pg1_select` reader - PG1 Select"]
143pub type PG1_SELECT_R = crate::FieldReader<PG1_SELECT_A>;
144#[doc = "PG1 Select\n\nValue on reset: 0"]
145#[derive(Clone, Copy, Debug, PartialEq, Eq)]
146#[repr(u8)]
147pub enum PG1_SELECT_A {
148    #[doc = "0: `0`"]
149    INPUT = 0,
150    #[doc = "2: `10`"]
151    SDC1_CMD = 2,
152    #[doc = "4: `100`"]
153    RGMII_RXD0_RMII_RXD0 = 4,
154    #[doc = "14: `1110`"]
155    PG_EINT1 = 14,
156    #[doc = "1: `1`"]
157    OUTPUT = 1,
158    #[doc = "3: `11`"]
159    UART3_RX = 3,
160    #[doc = "5: `101`"]
161    PWM6 = 5,
162    #[doc = "15: `1111`"]
163    IO_DISABLE = 15,
164}
165impl From<PG1_SELECT_A> for u8 {
166    #[inline(always)]
167    fn from(variant: PG1_SELECT_A) -> Self {
168        variant as _
169    }
170}
171impl crate::FieldSpec for PG1_SELECT_A {
172    type Ux = u8;
173}
174impl PG1_SELECT_R {
175    #[doc = "Get enumerated values variant"]
176    #[inline(always)]
177    pub const fn variant(&self) -> Option<PG1_SELECT_A> {
178        match self.bits {
179            0 => Some(PG1_SELECT_A::INPUT),
180            2 => Some(PG1_SELECT_A::SDC1_CMD),
181            4 => Some(PG1_SELECT_A::RGMII_RXD0_RMII_RXD0),
182            14 => Some(PG1_SELECT_A::PG_EINT1),
183            1 => Some(PG1_SELECT_A::OUTPUT),
184            3 => Some(PG1_SELECT_A::UART3_RX),
185            5 => Some(PG1_SELECT_A::PWM6),
186            15 => Some(PG1_SELECT_A::IO_DISABLE),
187            _ => None,
188        }
189    }
190    #[doc = "`0`"]
191    #[inline(always)]
192    pub fn is_input(&self) -> bool {
193        *self == PG1_SELECT_A::INPUT
194    }
195    #[doc = "`10`"]
196    #[inline(always)]
197    pub fn is_sdc1_cmd(&self) -> bool {
198        *self == PG1_SELECT_A::SDC1_CMD
199    }
200    #[doc = "`100`"]
201    #[inline(always)]
202    pub fn is_rgmii_rxd0_rmii_rxd0(&self) -> bool {
203        *self == PG1_SELECT_A::RGMII_RXD0_RMII_RXD0
204    }
205    #[doc = "`1110`"]
206    #[inline(always)]
207    pub fn is_pg_eint1(&self) -> bool {
208        *self == PG1_SELECT_A::PG_EINT1
209    }
210    #[doc = "`1`"]
211    #[inline(always)]
212    pub fn is_output(&self) -> bool {
213        *self == PG1_SELECT_A::OUTPUT
214    }
215    #[doc = "`11`"]
216    #[inline(always)]
217    pub fn is_uart3_rx(&self) -> bool {
218        *self == PG1_SELECT_A::UART3_RX
219    }
220    #[doc = "`101`"]
221    #[inline(always)]
222    pub fn is_pwm6(&self) -> bool {
223        *self == PG1_SELECT_A::PWM6
224    }
225    #[doc = "`1111`"]
226    #[inline(always)]
227    pub fn is_io_disable(&self) -> bool {
228        *self == PG1_SELECT_A::IO_DISABLE
229    }
230}
231#[doc = "Field `pg1_select` writer - PG1 Select"]
232pub type PG1_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG1_SELECT_A>;
233impl<'a, REG> PG1_SELECT_W<'a, REG>
234where
235    REG: crate::Writable + crate::RegisterSpec,
236    REG::Ux: From<u8>,
237{
238    #[doc = "`0`"]
239    #[inline(always)]
240    pub fn input(self) -> &'a mut crate::W<REG> {
241        self.variant(PG1_SELECT_A::INPUT)
242    }
243    #[doc = "`10`"]
244    #[inline(always)]
245    pub fn sdc1_cmd(self) -> &'a mut crate::W<REG> {
246        self.variant(PG1_SELECT_A::SDC1_CMD)
247    }
248    #[doc = "`100`"]
249    #[inline(always)]
250    pub fn rgmii_rxd0_rmii_rxd0(self) -> &'a mut crate::W<REG> {
251        self.variant(PG1_SELECT_A::RGMII_RXD0_RMII_RXD0)
252    }
253    #[doc = "`1110`"]
254    #[inline(always)]
255    pub fn pg_eint1(self) -> &'a mut crate::W<REG> {
256        self.variant(PG1_SELECT_A::PG_EINT1)
257    }
258    #[doc = "`1`"]
259    #[inline(always)]
260    pub fn output(self) -> &'a mut crate::W<REG> {
261        self.variant(PG1_SELECT_A::OUTPUT)
262    }
263    #[doc = "`11`"]
264    #[inline(always)]
265    pub fn uart3_rx(self) -> &'a mut crate::W<REG> {
266        self.variant(PG1_SELECT_A::UART3_RX)
267    }
268    #[doc = "`101`"]
269    #[inline(always)]
270    pub fn pwm6(self) -> &'a mut crate::W<REG> {
271        self.variant(PG1_SELECT_A::PWM6)
272    }
273    #[doc = "`1111`"]
274    #[inline(always)]
275    pub fn io_disable(self) -> &'a mut crate::W<REG> {
276        self.variant(PG1_SELECT_A::IO_DISABLE)
277    }
278}
279#[doc = "Field `pg2_select` reader - PG2 Select"]
280pub type PG2_SELECT_R = crate::FieldReader<PG2_SELECT_A>;
281#[doc = "PG2 Select\n\nValue on reset: 0"]
282#[derive(Clone, Copy, Debug, PartialEq, Eq)]
283#[repr(u8)]
284pub enum PG2_SELECT_A {
285    #[doc = "0: `0`"]
286    INPUT = 0,
287    #[doc = "2: `10`"]
288    SDC1_D0 = 2,
289    #[doc = "4: `100`"]
290    RGMII_RXD1_RMII_RXD1 = 4,
291    #[doc = "14: `1110`"]
292    PG_EINT2 = 14,
293    #[doc = "1: `1`"]
294    OUTPUT = 1,
295    #[doc = "3: `11`"]
296    UART3_RTS = 3,
297    #[doc = "5: `101`"]
298    UART4_TX = 5,
299    #[doc = "15: `1111`"]
300    IO_DISABLE = 15,
301}
302impl From<PG2_SELECT_A> for u8 {
303    #[inline(always)]
304    fn from(variant: PG2_SELECT_A) -> Self {
305        variant as _
306    }
307}
308impl crate::FieldSpec for PG2_SELECT_A {
309    type Ux = u8;
310}
311impl PG2_SELECT_R {
312    #[doc = "Get enumerated values variant"]
313    #[inline(always)]
314    pub const fn variant(&self) -> Option<PG2_SELECT_A> {
315        match self.bits {
316            0 => Some(PG2_SELECT_A::INPUT),
317            2 => Some(PG2_SELECT_A::SDC1_D0),
318            4 => Some(PG2_SELECT_A::RGMII_RXD1_RMII_RXD1),
319            14 => Some(PG2_SELECT_A::PG_EINT2),
320            1 => Some(PG2_SELECT_A::OUTPUT),
321            3 => Some(PG2_SELECT_A::UART3_RTS),
322            5 => Some(PG2_SELECT_A::UART4_TX),
323            15 => Some(PG2_SELECT_A::IO_DISABLE),
324            _ => None,
325        }
326    }
327    #[doc = "`0`"]
328    #[inline(always)]
329    pub fn is_input(&self) -> bool {
330        *self == PG2_SELECT_A::INPUT
331    }
332    #[doc = "`10`"]
333    #[inline(always)]
334    pub fn is_sdc1_d0(&self) -> bool {
335        *self == PG2_SELECT_A::SDC1_D0
336    }
337    #[doc = "`100`"]
338    #[inline(always)]
339    pub fn is_rgmii_rxd1_rmii_rxd1(&self) -> bool {
340        *self == PG2_SELECT_A::RGMII_RXD1_RMII_RXD1
341    }
342    #[doc = "`1110`"]
343    #[inline(always)]
344    pub fn is_pg_eint2(&self) -> bool {
345        *self == PG2_SELECT_A::PG_EINT2
346    }
347    #[doc = "`1`"]
348    #[inline(always)]
349    pub fn is_output(&self) -> bool {
350        *self == PG2_SELECT_A::OUTPUT
351    }
352    #[doc = "`11`"]
353    #[inline(always)]
354    pub fn is_uart3_rts(&self) -> bool {
355        *self == PG2_SELECT_A::UART3_RTS
356    }
357    #[doc = "`101`"]
358    #[inline(always)]
359    pub fn is_uart4_tx(&self) -> bool {
360        *self == PG2_SELECT_A::UART4_TX
361    }
362    #[doc = "`1111`"]
363    #[inline(always)]
364    pub fn is_io_disable(&self) -> bool {
365        *self == PG2_SELECT_A::IO_DISABLE
366    }
367}
368#[doc = "Field `pg2_select` writer - PG2 Select"]
369pub type PG2_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG2_SELECT_A>;
370impl<'a, REG> PG2_SELECT_W<'a, REG>
371where
372    REG: crate::Writable + crate::RegisterSpec,
373    REG::Ux: From<u8>,
374{
375    #[doc = "`0`"]
376    #[inline(always)]
377    pub fn input(self) -> &'a mut crate::W<REG> {
378        self.variant(PG2_SELECT_A::INPUT)
379    }
380    #[doc = "`10`"]
381    #[inline(always)]
382    pub fn sdc1_d0(self) -> &'a mut crate::W<REG> {
383        self.variant(PG2_SELECT_A::SDC1_D0)
384    }
385    #[doc = "`100`"]
386    #[inline(always)]
387    pub fn rgmii_rxd1_rmii_rxd1(self) -> &'a mut crate::W<REG> {
388        self.variant(PG2_SELECT_A::RGMII_RXD1_RMII_RXD1)
389    }
390    #[doc = "`1110`"]
391    #[inline(always)]
392    pub fn pg_eint2(self) -> &'a mut crate::W<REG> {
393        self.variant(PG2_SELECT_A::PG_EINT2)
394    }
395    #[doc = "`1`"]
396    #[inline(always)]
397    pub fn output(self) -> &'a mut crate::W<REG> {
398        self.variant(PG2_SELECT_A::OUTPUT)
399    }
400    #[doc = "`11`"]
401    #[inline(always)]
402    pub fn uart3_rts(self) -> &'a mut crate::W<REG> {
403        self.variant(PG2_SELECT_A::UART3_RTS)
404    }
405    #[doc = "`101`"]
406    #[inline(always)]
407    pub fn uart4_tx(self) -> &'a mut crate::W<REG> {
408        self.variant(PG2_SELECT_A::UART4_TX)
409    }
410    #[doc = "`1111`"]
411    #[inline(always)]
412    pub fn io_disable(self) -> &'a mut crate::W<REG> {
413        self.variant(PG2_SELECT_A::IO_DISABLE)
414    }
415}
416#[doc = "Field `pg3_select` reader - PG3 Select"]
417pub type PG3_SELECT_R = crate::FieldReader<PG3_SELECT_A>;
418#[doc = "PG3 Select\n\nValue on reset: 0"]
419#[derive(Clone, Copy, Debug, PartialEq, Eq)]
420#[repr(u8)]
421pub enum PG3_SELECT_A {
422    #[doc = "0: `0`"]
423    INPUT = 0,
424    #[doc = "2: `10`"]
425    SDC1_D1 = 2,
426    #[doc = "4: `100`"]
427    RGMII_TXCK_RMII_TXCK = 4,
428    #[doc = "14: `1110`"]
429    PG_EINT3 = 14,
430    #[doc = "1: `1`"]
431    OUTPUT = 1,
432    #[doc = "3: `11`"]
433    UART3_CTS = 3,
434    #[doc = "5: `101`"]
435    UART4_RX = 5,
436    #[doc = "15: `1111`"]
437    IO_DISABLE = 15,
438}
439impl From<PG3_SELECT_A> for u8 {
440    #[inline(always)]
441    fn from(variant: PG3_SELECT_A) -> Self {
442        variant as _
443    }
444}
445impl crate::FieldSpec for PG3_SELECT_A {
446    type Ux = u8;
447}
448impl PG3_SELECT_R {
449    #[doc = "Get enumerated values variant"]
450    #[inline(always)]
451    pub const fn variant(&self) -> Option<PG3_SELECT_A> {
452        match self.bits {
453            0 => Some(PG3_SELECT_A::INPUT),
454            2 => Some(PG3_SELECT_A::SDC1_D1),
455            4 => Some(PG3_SELECT_A::RGMII_TXCK_RMII_TXCK),
456            14 => Some(PG3_SELECT_A::PG_EINT3),
457            1 => Some(PG3_SELECT_A::OUTPUT),
458            3 => Some(PG3_SELECT_A::UART3_CTS),
459            5 => Some(PG3_SELECT_A::UART4_RX),
460            15 => Some(PG3_SELECT_A::IO_DISABLE),
461            _ => None,
462        }
463    }
464    #[doc = "`0`"]
465    #[inline(always)]
466    pub fn is_input(&self) -> bool {
467        *self == PG3_SELECT_A::INPUT
468    }
469    #[doc = "`10`"]
470    #[inline(always)]
471    pub fn is_sdc1_d1(&self) -> bool {
472        *self == PG3_SELECT_A::SDC1_D1
473    }
474    #[doc = "`100`"]
475    #[inline(always)]
476    pub fn is_rgmii_txck_rmii_txck(&self) -> bool {
477        *self == PG3_SELECT_A::RGMII_TXCK_RMII_TXCK
478    }
479    #[doc = "`1110`"]
480    #[inline(always)]
481    pub fn is_pg_eint3(&self) -> bool {
482        *self == PG3_SELECT_A::PG_EINT3
483    }
484    #[doc = "`1`"]
485    #[inline(always)]
486    pub fn is_output(&self) -> bool {
487        *self == PG3_SELECT_A::OUTPUT
488    }
489    #[doc = "`11`"]
490    #[inline(always)]
491    pub fn is_uart3_cts(&self) -> bool {
492        *self == PG3_SELECT_A::UART3_CTS
493    }
494    #[doc = "`101`"]
495    #[inline(always)]
496    pub fn is_uart4_rx(&self) -> bool {
497        *self == PG3_SELECT_A::UART4_RX
498    }
499    #[doc = "`1111`"]
500    #[inline(always)]
501    pub fn is_io_disable(&self) -> bool {
502        *self == PG3_SELECT_A::IO_DISABLE
503    }
504}
505#[doc = "Field `pg3_select` writer - PG3 Select"]
506pub type PG3_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG3_SELECT_A>;
507impl<'a, REG> PG3_SELECT_W<'a, REG>
508where
509    REG: crate::Writable + crate::RegisterSpec,
510    REG::Ux: From<u8>,
511{
512    #[doc = "`0`"]
513    #[inline(always)]
514    pub fn input(self) -> &'a mut crate::W<REG> {
515        self.variant(PG3_SELECT_A::INPUT)
516    }
517    #[doc = "`10`"]
518    #[inline(always)]
519    pub fn sdc1_d1(self) -> &'a mut crate::W<REG> {
520        self.variant(PG3_SELECT_A::SDC1_D1)
521    }
522    #[doc = "`100`"]
523    #[inline(always)]
524    pub fn rgmii_txck_rmii_txck(self) -> &'a mut crate::W<REG> {
525        self.variant(PG3_SELECT_A::RGMII_TXCK_RMII_TXCK)
526    }
527    #[doc = "`1110`"]
528    #[inline(always)]
529    pub fn pg_eint3(self) -> &'a mut crate::W<REG> {
530        self.variant(PG3_SELECT_A::PG_EINT3)
531    }
532    #[doc = "`1`"]
533    #[inline(always)]
534    pub fn output(self) -> &'a mut crate::W<REG> {
535        self.variant(PG3_SELECT_A::OUTPUT)
536    }
537    #[doc = "`11`"]
538    #[inline(always)]
539    pub fn uart3_cts(self) -> &'a mut crate::W<REG> {
540        self.variant(PG3_SELECT_A::UART3_CTS)
541    }
542    #[doc = "`101`"]
543    #[inline(always)]
544    pub fn uart4_rx(self) -> &'a mut crate::W<REG> {
545        self.variant(PG3_SELECT_A::UART4_RX)
546    }
547    #[doc = "`1111`"]
548    #[inline(always)]
549    pub fn io_disable(self) -> &'a mut crate::W<REG> {
550        self.variant(PG3_SELECT_A::IO_DISABLE)
551    }
552}
553#[doc = "Field `pg4_select` reader - PG4 Select"]
554pub type PG4_SELECT_R = crate::FieldReader<PG4_SELECT_A>;
555#[doc = "PG4 Select\n\nValue on reset: 0"]
556#[derive(Clone, Copy, Debug, PartialEq, Eq)]
557#[repr(u8)]
558pub enum PG4_SELECT_A {
559    #[doc = "0: `0`"]
560    INPUT = 0,
561    #[doc = "2: `10`"]
562    SDC1_D2 = 2,
563    #[doc = "4: `100`"]
564    RGMII_TXD0_RMII_TXD0 = 4,
565    #[doc = "14: `1110`"]
566    PG_EINT4 = 14,
567    #[doc = "1: `1`"]
568    OUTPUT = 1,
569    #[doc = "3: `11`"]
570    UART5_TX = 3,
571    #[doc = "5: `101`"]
572    PWM5 = 5,
573    #[doc = "15: `1111`"]
574    IO_DISABLE = 15,
575}
576impl From<PG4_SELECT_A> for u8 {
577    #[inline(always)]
578    fn from(variant: PG4_SELECT_A) -> Self {
579        variant as _
580    }
581}
582impl crate::FieldSpec for PG4_SELECT_A {
583    type Ux = u8;
584}
585impl PG4_SELECT_R {
586    #[doc = "Get enumerated values variant"]
587    #[inline(always)]
588    pub const fn variant(&self) -> Option<PG4_SELECT_A> {
589        match self.bits {
590            0 => Some(PG4_SELECT_A::INPUT),
591            2 => Some(PG4_SELECT_A::SDC1_D2),
592            4 => Some(PG4_SELECT_A::RGMII_TXD0_RMII_TXD0),
593            14 => Some(PG4_SELECT_A::PG_EINT4),
594            1 => Some(PG4_SELECT_A::OUTPUT),
595            3 => Some(PG4_SELECT_A::UART5_TX),
596            5 => Some(PG4_SELECT_A::PWM5),
597            15 => Some(PG4_SELECT_A::IO_DISABLE),
598            _ => None,
599        }
600    }
601    #[doc = "`0`"]
602    #[inline(always)]
603    pub fn is_input(&self) -> bool {
604        *self == PG4_SELECT_A::INPUT
605    }
606    #[doc = "`10`"]
607    #[inline(always)]
608    pub fn is_sdc1_d2(&self) -> bool {
609        *self == PG4_SELECT_A::SDC1_D2
610    }
611    #[doc = "`100`"]
612    #[inline(always)]
613    pub fn is_rgmii_txd0_rmii_txd0(&self) -> bool {
614        *self == PG4_SELECT_A::RGMII_TXD0_RMII_TXD0
615    }
616    #[doc = "`1110`"]
617    #[inline(always)]
618    pub fn is_pg_eint4(&self) -> bool {
619        *self == PG4_SELECT_A::PG_EINT4
620    }
621    #[doc = "`1`"]
622    #[inline(always)]
623    pub fn is_output(&self) -> bool {
624        *self == PG4_SELECT_A::OUTPUT
625    }
626    #[doc = "`11`"]
627    #[inline(always)]
628    pub fn is_uart5_tx(&self) -> bool {
629        *self == PG4_SELECT_A::UART5_TX
630    }
631    #[doc = "`101`"]
632    #[inline(always)]
633    pub fn is_pwm5(&self) -> bool {
634        *self == PG4_SELECT_A::PWM5
635    }
636    #[doc = "`1111`"]
637    #[inline(always)]
638    pub fn is_io_disable(&self) -> bool {
639        *self == PG4_SELECT_A::IO_DISABLE
640    }
641}
642#[doc = "Field `pg4_select` writer - PG4 Select"]
643pub type PG4_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG4_SELECT_A>;
644impl<'a, REG> PG4_SELECT_W<'a, REG>
645where
646    REG: crate::Writable + crate::RegisterSpec,
647    REG::Ux: From<u8>,
648{
649    #[doc = "`0`"]
650    #[inline(always)]
651    pub fn input(self) -> &'a mut crate::W<REG> {
652        self.variant(PG4_SELECT_A::INPUT)
653    }
654    #[doc = "`10`"]
655    #[inline(always)]
656    pub fn sdc1_d2(self) -> &'a mut crate::W<REG> {
657        self.variant(PG4_SELECT_A::SDC1_D2)
658    }
659    #[doc = "`100`"]
660    #[inline(always)]
661    pub fn rgmii_txd0_rmii_txd0(self) -> &'a mut crate::W<REG> {
662        self.variant(PG4_SELECT_A::RGMII_TXD0_RMII_TXD0)
663    }
664    #[doc = "`1110`"]
665    #[inline(always)]
666    pub fn pg_eint4(self) -> &'a mut crate::W<REG> {
667        self.variant(PG4_SELECT_A::PG_EINT4)
668    }
669    #[doc = "`1`"]
670    #[inline(always)]
671    pub fn output(self) -> &'a mut crate::W<REG> {
672        self.variant(PG4_SELECT_A::OUTPUT)
673    }
674    #[doc = "`11`"]
675    #[inline(always)]
676    pub fn uart5_tx(self) -> &'a mut crate::W<REG> {
677        self.variant(PG4_SELECT_A::UART5_TX)
678    }
679    #[doc = "`101`"]
680    #[inline(always)]
681    pub fn pwm5(self) -> &'a mut crate::W<REG> {
682        self.variant(PG4_SELECT_A::PWM5)
683    }
684    #[doc = "`1111`"]
685    #[inline(always)]
686    pub fn io_disable(self) -> &'a mut crate::W<REG> {
687        self.variant(PG4_SELECT_A::IO_DISABLE)
688    }
689}
690#[doc = "Field `pg5_select` reader - PG5 Select"]
691pub type PG5_SELECT_R = crate::FieldReader<PG5_SELECT_A>;
692#[doc = "PG5 Select\n\nValue on reset: 0"]
693#[derive(Clone, Copy, Debug, PartialEq, Eq)]
694#[repr(u8)]
695pub enum PG5_SELECT_A {
696    #[doc = "0: `0`"]
697    INPUT = 0,
698    #[doc = "2: `10`"]
699    SDC1_D3 = 2,
700    #[doc = "4: `100`"]
701    RGMII_TXD1_RMII_TXD1 = 4,
702    #[doc = "14: `1110`"]
703    PG_EINT5 = 14,
704    #[doc = "1: `1`"]
705    OUTPUT = 1,
706    #[doc = "3: `11`"]
707    UART5_RX = 3,
708    #[doc = "5: `101`"]
709    PWM4 = 5,
710    #[doc = "15: `1111`"]
711    IO_DISABLE = 15,
712}
713impl From<PG5_SELECT_A> for u8 {
714    #[inline(always)]
715    fn from(variant: PG5_SELECT_A) -> Self {
716        variant as _
717    }
718}
719impl crate::FieldSpec for PG5_SELECT_A {
720    type Ux = u8;
721}
722impl PG5_SELECT_R {
723    #[doc = "Get enumerated values variant"]
724    #[inline(always)]
725    pub const fn variant(&self) -> Option<PG5_SELECT_A> {
726        match self.bits {
727            0 => Some(PG5_SELECT_A::INPUT),
728            2 => Some(PG5_SELECT_A::SDC1_D3),
729            4 => Some(PG5_SELECT_A::RGMII_TXD1_RMII_TXD1),
730            14 => Some(PG5_SELECT_A::PG_EINT5),
731            1 => Some(PG5_SELECT_A::OUTPUT),
732            3 => Some(PG5_SELECT_A::UART5_RX),
733            5 => Some(PG5_SELECT_A::PWM4),
734            15 => Some(PG5_SELECT_A::IO_DISABLE),
735            _ => None,
736        }
737    }
738    #[doc = "`0`"]
739    #[inline(always)]
740    pub fn is_input(&self) -> bool {
741        *self == PG5_SELECT_A::INPUT
742    }
743    #[doc = "`10`"]
744    #[inline(always)]
745    pub fn is_sdc1_d3(&self) -> bool {
746        *self == PG5_SELECT_A::SDC1_D3
747    }
748    #[doc = "`100`"]
749    #[inline(always)]
750    pub fn is_rgmii_txd1_rmii_txd1(&self) -> bool {
751        *self == PG5_SELECT_A::RGMII_TXD1_RMII_TXD1
752    }
753    #[doc = "`1110`"]
754    #[inline(always)]
755    pub fn is_pg_eint5(&self) -> bool {
756        *self == PG5_SELECT_A::PG_EINT5
757    }
758    #[doc = "`1`"]
759    #[inline(always)]
760    pub fn is_output(&self) -> bool {
761        *self == PG5_SELECT_A::OUTPUT
762    }
763    #[doc = "`11`"]
764    #[inline(always)]
765    pub fn is_uart5_rx(&self) -> bool {
766        *self == PG5_SELECT_A::UART5_RX
767    }
768    #[doc = "`101`"]
769    #[inline(always)]
770    pub fn is_pwm4(&self) -> bool {
771        *self == PG5_SELECT_A::PWM4
772    }
773    #[doc = "`1111`"]
774    #[inline(always)]
775    pub fn is_io_disable(&self) -> bool {
776        *self == PG5_SELECT_A::IO_DISABLE
777    }
778}
779#[doc = "Field `pg5_select` writer - PG5 Select"]
780pub type PG5_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG5_SELECT_A>;
781impl<'a, REG> PG5_SELECT_W<'a, REG>
782where
783    REG: crate::Writable + crate::RegisterSpec,
784    REG::Ux: From<u8>,
785{
786    #[doc = "`0`"]
787    #[inline(always)]
788    pub fn input(self) -> &'a mut crate::W<REG> {
789        self.variant(PG5_SELECT_A::INPUT)
790    }
791    #[doc = "`10`"]
792    #[inline(always)]
793    pub fn sdc1_d3(self) -> &'a mut crate::W<REG> {
794        self.variant(PG5_SELECT_A::SDC1_D3)
795    }
796    #[doc = "`100`"]
797    #[inline(always)]
798    pub fn rgmii_txd1_rmii_txd1(self) -> &'a mut crate::W<REG> {
799        self.variant(PG5_SELECT_A::RGMII_TXD1_RMII_TXD1)
800    }
801    #[doc = "`1110`"]
802    #[inline(always)]
803    pub fn pg_eint5(self) -> &'a mut crate::W<REG> {
804        self.variant(PG5_SELECT_A::PG_EINT5)
805    }
806    #[doc = "`1`"]
807    #[inline(always)]
808    pub fn output(self) -> &'a mut crate::W<REG> {
809        self.variant(PG5_SELECT_A::OUTPUT)
810    }
811    #[doc = "`11`"]
812    #[inline(always)]
813    pub fn uart5_rx(self) -> &'a mut crate::W<REG> {
814        self.variant(PG5_SELECT_A::UART5_RX)
815    }
816    #[doc = "`101`"]
817    #[inline(always)]
818    pub fn pwm4(self) -> &'a mut crate::W<REG> {
819        self.variant(PG5_SELECT_A::PWM4)
820    }
821    #[doc = "`1111`"]
822    #[inline(always)]
823    pub fn io_disable(self) -> &'a mut crate::W<REG> {
824        self.variant(PG5_SELECT_A::IO_DISABLE)
825    }
826}
827#[doc = "Field `pg6_select` reader - PG6 Select"]
828pub type PG6_SELECT_R = crate::FieldReader<PG6_SELECT_A>;
829#[doc = "PG6 Select\n\nValue on reset: 0"]
830#[derive(Clone, Copy, Debug, PartialEq, Eq)]
831#[repr(u8)]
832pub enum PG6_SELECT_A {
833    #[doc = "0: `0`"]
834    INPUT = 0,
835    #[doc = "2: `10`"]
836    UART1_TX = 2,
837    #[doc = "4: `100`"]
838    RGMII_TXD2 = 4,
839    #[doc = "14: `1110`"]
840    PG_EINT6 = 14,
841    #[doc = "1: `1`"]
842    OUTPUT = 1,
843    #[doc = "3: `11`"]
844    TWI2_SCK = 3,
845    #[doc = "5: `101`"]
846    PWM1 = 5,
847    #[doc = "15: `1111`"]
848    IO_DISABLE = 15,
849}
850impl From<PG6_SELECT_A> for u8 {
851    #[inline(always)]
852    fn from(variant: PG6_SELECT_A) -> Self {
853        variant as _
854    }
855}
856impl crate::FieldSpec for PG6_SELECT_A {
857    type Ux = u8;
858}
859impl PG6_SELECT_R {
860    #[doc = "Get enumerated values variant"]
861    #[inline(always)]
862    pub const fn variant(&self) -> Option<PG6_SELECT_A> {
863        match self.bits {
864            0 => Some(PG6_SELECT_A::INPUT),
865            2 => Some(PG6_SELECT_A::UART1_TX),
866            4 => Some(PG6_SELECT_A::RGMII_TXD2),
867            14 => Some(PG6_SELECT_A::PG_EINT6),
868            1 => Some(PG6_SELECT_A::OUTPUT),
869            3 => Some(PG6_SELECT_A::TWI2_SCK),
870            5 => Some(PG6_SELECT_A::PWM1),
871            15 => Some(PG6_SELECT_A::IO_DISABLE),
872            _ => None,
873        }
874    }
875    #[doc = "`0`"]
876    #[inline(always)]
877    pub fn is_input(&self) -> bool {
878        *self == PG6_SELECT_A::INPUT
879    }
880    #[doc = "`10`"]
881    #[inline(always)]
882    pub fn is_uart1_tx(&self) -> bool {
883        *self == PG6_SELECT_A::UART1_TX
884    }
885    #[doc = "`100`"]
886    #[inline(always)]
887    pub fn is_rgmii_txd2(&self) -> bool {
888        *self == PG6_SELECT_A::RGMII_TXD2
889    }
890    #[doc = "`1110`"]
891    #[inline(always)]
892    pub fn is_pg_eint6(&self) -> bool {
893        *self == PG6_SELECT_A::PG_EINT6
894    }
895    #[doc = "`1`"]
896    #[inline(always)]
897    pub fn is_output(&self) -> bool {
898        *self == PG6_SELECT_A::OUTPUT
899    }
900    #[doc = "`11`"]
901    #[inline(always)]
902    pub fn is_twi2_sck(&self) -> bool {
903        *self == PG6_SELECT_A::TWI2_SCK
904    }
905    #[doc = "`101`"]
906    #[inline(always)]
907    pub fn is_pwm1(&self) -> bool {
908        *self == PG6_SELECT_A::PWM1
909    }
910    #[doc = "`1111`"]
911    #[inline(always)]
912    pub fn is_io_disable(&self) -> bool {
913        *self == PG6_SELECT_A::IO_DISABLE
914    }
915}
916#[doc = "Field `pg6_select` writer - PG6 Select"]
917pub type PG6_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG6_SELECT_A>;
918impl<'a, REG> PG6_SELECT_W<'a, REG>
919where
920    REG: crate::Writable + crate::RegisterSpec,
921    REG::Ux: From<u8>,
922{
923    #[doc = "`0`"]
924    #[inline(always)]
925    pub fn input(self) -> &'a mut crate::W<REG> {
926        self.variant(PG6_SELECT_A::INPUT)
927    }
928    #[doc = "`10`"]
929    #[inline(always)]
930    pub fn uart1_tx(self) -> &'a mut crate::W<REG> {
931        self.variant(PG6_SELECT_A::UART1_TX)
932    }
933    #[doc = "`100`"]
934    #[inline(always)]
935    pub fn rgmii_txd2(self) -> &'a mut crate::W<REG> {
936        self.variant(PG6_SELECT_A::RGMII_TXD2)
937    }
938    #[doc = "`1110`"]
939    #[inline(always)]
940    pub fn pg_eint6(self) -> &'a mut crate::W<REG> {
941        self.variant(PG6_SELECT_A::PG_EINT6)
942    }
943    #[doc = "`1`"]
944    #[inline(always)]
945    pub fn output(self) -> &'a mut crate::W<REG> {
946        self.variant(PG6_SELECT_A::OUTPUT)
947    }
948    #[doc = "`11`"]
949    #[inline(always)]
950    pub fn twi2_sck(self) -> &'a mut crate::W<REG> {
951        self.variant(PG6_SELECT_A::TWI2_SCK)
952    }
953    #[doc = "`101`"]
954    #[inline(always)]
955    pub fn pwm1(self) -> &'a mut crate::W<REG> {
956        self.variant(PG6_SELECT_A::PWM1)
957    }
958    #[doc = "`1111`"]
959    #[inline(always)]
960    pub fn io_disable(self) -> &'a mut crate::W<REG> {
961        self.variant(PG6_SELECT_A::IO_DISABLE)
962    }
963}
964#[doc = "Field `pg7_select` reader - PG7 Select"]
965pub type PG7_SELECT_R = crate::FieldReader<PG7_SELECT_A>;
966#[doc = "PG7 Select\n\nValue on reset: 0"]
967#[derive(Clone, Copy, Debug, PartialEq, Eq)]
968#[repr(u8)]
969pub enum PG7_SELECT_A {
970    #[doc = "0: `0`"]
971    INPUT = 0,
972    #[doc = "2: `10`"]
973    UART1_RX = 2,
974    #[doc = "4: `100`"]
975    RGMII_TXD3 = 4,
976    #[doc = "14: `1110`"]
977    PG_EINT7 = 14,
978    #[doc = "1: `1`"]
979    OUTPUT = 1,
980    #[doc = "3: `11`"]
981    TWI2_SDA = 3,
982    #[doc = "5: `101`"]
983    OWA_IN = 5,
984    #[doc = "15: `1111`"]
985    IO_DISABLE = 15,
986}
987impl From<PG7_SELECT_A> for u8 {
988    #[inline(always)]
989    fn from(variant: PG7_SELECT_A) -> Self {
990        variant as _
991    }
992}
993impl crate::FieldSpec for PG7_SELECT_A {
994    type Ux = u8;
995}
996impl PG7_SELECT_R {
997    #[doc = "Get enumerated values variant"]
998    #[inline(always)]
999    pub const fn variant(&self) -> Option<PG7_SELECT_A> {
1000        match self.bits {
1001            0 => Some(PG7_SELECT_A::INPUT),
1002            2 => Some(PG7_SELECT_A::UART1_RX),
1003            4 => Some(PG7_SELECT_A::RGMII_TXD3),
1004            14 => Some(PG7_SELECT_A::PG_EINT7),
1005            1 => Some(PG7_SELECT_A::OUTPUT),
1006            3 => Some(PG7_SELECT_A::TWI2_SDA),
1007            5 => Some(PG7_SELECT_A::OWA_IN),
1008            15 => Some(PG7_SELECT_A::IO_DISABLE),
1009            _ => None,
1010        }
1011    }
1012    #[doc = "`0`"]
1013    #[inline(always)]
1014    pub fn is_input(&self) -> bool {
1015        *self == PG7_SELECT_A::INPUT
1016    }
1017    #[doc = "`10`"]
1018    #[inline(always)]
1019    pub fn is_uart1_rx(&self) -> bool {
1020        *self == PG7_SELECT_A::UART1_RX
1021    }
1022    #[doc = "`100`"]
1023    #[inline(always)]
1024    pub fn is_rgmii_txd3(&self) -> bool {
1025        *self == PG7_SELECT_A::RGMII_TXD3
1026    }
1027    #[doc = "`1110`"]
1028    #[inline(always)]
1029    pub fn is_pg_eint7(&self) -> bool {
1030        *self == PG7_SELECT_A::PG_EINT7
1031    }
1032    #[doc = "`1`"]
1033    #[inline(always)]
1034    pub fn is_output(&self) -> bool {
1035        *self == PG7_SELECT_A::OUTPUT
1036    }
1037    #[doc = "`11`"]
1038    #[inline(always)]
1039    pub fn is_twi2_sda(&self) -> bool {
1040        *self == PG7_SELECT_A::TWI2_SDA
1041    }
1042    #[doc = "`101`"]
1043    #[inline(always)]
1044    pub fn is_owa_in(&self) -> bool {
1045        *self == PG7_SELECT_A::OWA_IN
1046    }
1047    #[doc = "`1111`"]
1048    #[inline(always)]
1049    pub fn is_io_disable(&self) -> bool {
1050        *self == PG7_SELECT_A::IO_DISABLE
1051    }
1052}
1053#[doc = "Field `pg7_select` writer - PG7 Select"]
1054pub type PG7_SELECT_W<'a, REG> = crate::FieldWriter<'a, REG, 4, PG7_SELECT_A>;
1055impl<'a, REG> PG7_SELECT_W<'a, REG>
1056where
1057    REG: crate::Writable + crate::RegisterSpec,
1058    REG::Ux: From<u8>,
1059{
1060    #[doc = "`0`"]
1061    #[inline(always)]
1062    pub fn input(self) -> &'a mut crate::W<REG> {
1063        self.variant(PG7_SELECT_A::INPUT)
1064    }
1065    #[doc = "`10`"]
1066    #[inline(always)]
1067    pub fn uart1_rx(self) -> &'a mut crate::W<REG> {
1068        self.variant(PG7_SELECT_A::UART1_RX)
1069    }
1070    #[doc = "`100`"]
1071    #[inline(always)]
1072    pub fn rgmii_txd3(self) -> &'a mut crate::W<REG> {
1073        self.variant(PG7_SELECT_A::RGMII_TXD3)
1074    }
1075    #[doc = "`1110`"]
1076    #[inline(always)]
1077    pub fn pg_eint7(self) -> &'a mut crate::W<REG> {
1078        self.variant(PG7_SELECT_A::PG_EINT7)
1079    }
1080    #[doc = "`1`"]
1081    #[inline(always)]
1082    pub fn output(self) -> &'a mut crate::W<REG> {
1083        self.variant(PG7_SELECT_A::OUTPUT)
1084    }
1085    #[doc = "`11`"]
1086    #[inline(always)]
1087    pub fn twi2_sda(self) -> &'a mut crate::W<REG> {
1088        self.variant(PG7_SELECT_A::TWI2_SDA)
1089    }
1090    #[doc = "`101`"]
1091    #[inline(always)]
1092    pub fn owa_in(self) -> &'a mut crate::W<REG> {
1093        self.variant(PG7_SELECT_A::OWA_IN)
1094    }
1095    #[doc = "`1111`"]
1096    #[inline(always)]
1097    pub fn io_disable(self) -> &'a mut crate::W<REG> {
1098        self.variant(PG7_SELECT_A::IO_DISABLE)
1099    }
1100}
1101impl R {
1102    #[doc = "Bits 0:3 - PG0 Select"]
1103    #[inline(always)]
1104    pub fn pg0_select(&self) -> PG0_SELECT_R {
1105        PG0_SELECT_R::new((self.bits & 0x0f) as u8)
1106    }
1107    #[doc = "Bits 4:7 - PG1 Select"]
1108    #[inline(always)]
1109    pub fn pg1_select(&self) -> PG1_SELECT_R {
1110        PG1_SELECT_R::new(((self.bits >> 4) & 0x0f) as u8)
1111    }
1112    #[doc = "Bits 8:11 - PG2 Select"]
1113    #[inline(always)]
1114    pub fn pg2_select(&self) -> PG2_SELECT_R {
1115        PG2_SELECT_R::new(((self.bits >> 8) & 0x0f) as u8)
1116    }
1117    #[doc = "Bits 12:15 - PG3 Select"]
1118    #[inline(always)]
1119    pub fn pg3_select(&self) -> PG3_SELECT_R {
1120        PG3_SELECT_R::new(((self.bits >> 12) & 0x0f) as u8)
1121    }
1122    #[doc = "Bits 16:19 - PG4 Select"]
1123    #[inline(always)]
1124    pub fn pg4_select(&self) -> PG4_SELECT_R {
1125        PG4_SELECT_R::new(((self.bits >> 16) & 0x0f) as u8)
1126    }
1127    #[doc = "Bits 20:23 - PG5 Select"]
1128    #[inline(always)]
1129    pub fn pg5_select(&self) -> PG5_SELECT_R {
1130        PG5_SELECT_R::new(((self.bits >> 20) & 0x0f) as u8)
1131    }
1132    #[doc = "Bits 24:27 - PG6 Select"]
1133    #[inline(always)]
1134    pub fn pg6_select(&self) -> PG6_SELECT_R {
1135        PG6_SELECT_R::new(((self.bits >> 24) & 0x0f) as u8)
1136    }
1137    #[doc = "Bits 28:31 - PG7 Select"]
1138    #[inline(always)]
1139    pub fn pg7_select(&self) -> PG7_SELECT_R {
1140        PG7_SELECT_R::new(((self.bits >> 28) & 0x0f) as u8)
1141    }
1142}
1143impl W {
1144    #[doc = "Bits 0:3 - PG0 Select"]
1145    #[inline(always)]
1146    #[must_use]
1147    pub fn pg0_select(&mut self) -> PG0_SELECT_W<PG_CFG0_SPEC> {
1148        PG0_SELECT_W::new(self, 0)
1149    }
1150    #[doc = "Bits 4:7 - PG1 Select"]
1151    #[inline(always)]
1152    #[must_use]
1153    pub fn pg1_select(&mut self) -> PG1_SELECT_W<PG_CFG0_SPEC> {
1154        PG1_SELECT_W::new(self, 4)
1155    }
1156    #[doc = "Bits 8:11 - PG2 Select"]
1157    #[inline(always)]
1158    #[must_use]
1159    pub fn pg2_select(&mut self) -> PG2_SELECT_W<PG_CFG0_SPEC> {
1160        PG2_SELECT_W::new(self, 8)
1161    }
1162    #[doc = "Bits 12:15 - PG3 Select"]
1163    #[inline(always)]
1164    #[must_use]
1165    pub fn pg3_select(&mut self) -> PG3_SELECT_W<PG_CFG0_SPEC> {
1166        PG3_SELECT_W::new(self, 12)
1167    }
1168    #[doc = "Bits 16:19 - PG4 Select"]
1169    #[inline(always)]
1170    #[must_use]
1171    pub fn pg4_select(&mut self) -> PG4_SELECT_W<PG_CFG0_SPEC> {
1172        PG4_SELECT_W::new(self, 16)
1173    }
1174    #[doc = "Bits 20:23 - PG5 Select"]
1175    #[inline(always)]
1176    #[must_use]
1177    pub fn pg5_select(&mut self) -> PG5_SELECT_W<PG_CFG0_SPEC> {
1178        PG5_SELECT_W::new(self, 20)
1179    }
1180    #[doc = "Bits 24:27 - PG6 Select"]
1181    #[inline(always)]
1182    #[must_use]
1183    pub fn pg6_select(&mut self) -> PG6_SELECT_W<PG_CFG0_SPEC> {
1184        PG6_SELECT_W::new(self, 24)
1185    }
1186    #[doc = "Bits 28:31 - PG7 Select"]
1187    #[inline(always)]
1188    #[must_use]
1189    pub fn pg7_select(&mut self) -> PG7_SELECT_W<PG_CFG0_SPEC> {
1190        PG7_SELECT_W::new(self, 28)
1191    }
1192    #[doc = r" Writes raw bits to the register."]
1193    #[doc = r""]
1194    #[doc = r" # Safety"]
1195    #[doc = r""]
1196    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
1197    #[inline(always)]
1198    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1199        self.bits = bits;
1200        self
1201    }
1202}
1203#[doc = "PG Configure Register 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pg_cfg0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pg_cfg0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
1204pub struct PG_CFG0_SPEC;
1205impl crate::RegisterSpec for PG_CFG0_SPEC {
1206    type Ux = u32;
1207}
1208#[doc = "`read()` method returns [`pg_cfg0::R`](R) reader structure"]
1209impl crate::Readable for PG_CFG0_SPEC {}
1210#[doc = "`write(|w| ..)` method takes [`pg_cfg0::W`](W) writer structure"]
1211impl crate::Writable for PG_CFG0_SPEC {
1212    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1213    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
1214}
1215#[doc = "`reset()` method sets pg_cfg0 to value 0"]
1216impl crate::Resettable for PG_CFG0_SPEC {
1217    const RESET_VALUE: Self::Ux = 0;
1218}
d1_pac/gpio/pg_cfg0.rs

d1_pac/gpio/
pg_cfg0.rs
