d1_pac/gpio/
pe_eint_deb.rs

1#[doc = "Register `pe_eint_deb` reader"]
2pub type R = crate::R<PE_EINT_DEB_SPEC>;
3#[doc = "Register `pe_eint_deb` writer"]
4pub type W = crate::W<PE_EINT_DEB_SPEC>;
5#[doc = "Field `pio_int_clk_select` reader - PIO Interrupt Clock Select"]
6pub type PIO_INT_CLK_SELECT_R = crate::BitReader<PIO_INT_CLK_SELECT_A>;
7#[doc = "PIO Interrupt Clock Select\n\nValue on reset: 0"]
8#[derive(Clone, Copy, Debug, PartialEq, Eq)]
9pub enum PIO_INT_CLK_SELECT_A {
10    #[doc = "0: `0`"]
11    LOSC_32K_HZ = 0,
12    #[doc = "1: `1`"]
13    HOSC_24M_HZ = 1,
14}
15impl From<PIO_INT_CLK_SELECT_A> for bool {
16    #[inline(always)]
17    fn from(variant: PIO_INT_CLK_SELECT_A) -> Self {
18        variant as u8 != 0
19    }
20}
21impl PIO_INT_CLK_SELECT_R {
22    #[doc = "Get enumerated values variant"]
23    #[inline(always)]
24    pub const fn variant(&self) -> PIO_INT_CLK_SELECT_A {
25        match self.bits {
26            false => PIO_INT_CLK_SELECT_A::LOSC_32K_HZ,
27            true => PIO_INT_CLK_SELECT_A::HOSC_24M_HZ,
28        }
29    }
30    #[doc = "`0`"]
31    #[inline(always)]
32    pub fn is_losc_32k_hz(&self) -> bool {
33        *self == PIO_INT_CLK_SELECT_A::LOSC_32K_HZ
34    }
35    #[doc = "`1`"]
36    #[inline(always)]
37    pub fn is_hosc_24m_hz(&self) -> bool {
38        *self == PIO_INT_CLK_SELECT_A::HOSC_24M_HZ
39    }
40}
41#[doc = "Field `pio_int_clk_select` writer - PIO Interrupt Clock Select"]
42pub type PIO_INT_CLK_SELECT_W<'a, REG> = crate::BitWriter<'a, REG, PIO_INT_CLK_SELECT_A>;
43impl<'a, REG> PIO_INT_CLK_SELECT_W<'a, REG>
44where
45    REG: crate::Writable + crate::RegisterSpec,
46{
47    #[doc = "`0`"]
48    #[inline(always)]
49    pub fn losc_32k_hz(self) -> &'a mut crate::W<REG> {
50        self.variant(PIO_INT_CLK_SELECT_A::LOSC_32K_HZ)
51    }
52    #[doc = "`1`"]
53    #[inline(always)]
54    pub fn hosc_24m_hz(self) -> &'a mut crate::W<REG> {
55        self.variant(PIO_INT_CLK_SELECT_A::HOSC_24M_HZ)
56    }
57}
58#[doc = "Field `deb_clk_pre_scale` reader - Debounce Clock Pre_scale n"]
59pub type DEB_CLK_PRE_SCALE_R = crate::FieldReader;
60#[doc = "Field `deb_clk_pre_scale` writer - Debounce Clock Pre_scale n"]
61pub type DEB_CLK_PRE_SCALE_W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
62impl R {
63    #[doc = "Bit 0 - PIO Interrupt Clock Select"]
64    #[inline(always)]
65    pub fn pio_int_clk_select(&self) -> PIO_INT_CLK_SELECT_R {
66        PIO_INT_CLK_SELECT_R::new((self.bits & 1) != 0)
67    }
68    #[doc = "Bits 4:6 - Debounce Clock Pre_scale n"]
69    #[inline(always)]
70    pub fn deb_clk_pre_scale(&self) -> DEB_CLK_PRE_SCALE_R {
71        DEB_CLK_PRE_SCALE_R::new(((self.bits >> 4) & 7) as u8)
72    }
73}
74impl W {
75    #[doc = "Bit 0 - PIO Interrupt Clock Select"]
76    #[inline(always)]
77    #[must_use]
78    pub fn pio_int_clk_select(&mut self) -> PIO_INT_CLK_SELECT_W<PE_EINT_DEB_SPEC> {
79        PIO_INT_CLK_SELECT_W::new(self, 0)
80    }
81    #[doc = "Bits 4:6 - Debounce Clock Pre_scale n"]
82    #[inline(always)]
83    #[must_use]
84    pub fn deb_clk_pre_scale(&mut self) -> DEB_CLK_PRE_SCALE_W<PE_EINT_DEB_SPEC> {
85        DEB_CLK_PRE_SCALE_W::new(self, 4)
86    }
87    #[doc = r" Writes raw bits to the register."]
88    #[doc = r""]
89    #[doc = r" # Safety"]
90    #[doc = r""]
91    #[doc = r" Passing incorrect value can cause undefined behaviour. See reference manual"]
92    #[inline(always)]
93    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
94        self.bits = bits;
95        self
96    }
97}
98#[doc = "PE External Interrupt Debounce Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`pe_eint_deb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`pe_eint_deb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
99pub struct PE_EINT_DEB_SPEC;
100impl crate::RegisterSpec for PE_EINT_DEB_SPEC {
101    type Ux = u32;
102}
103#[doc = "`read()` method returns [`pe_eint_deb::R`](R) reader structure"]
104impl crate::Readable for PE_EINT_DEB_SPEC {}
105#[doc = "`write(|w| ..)` method takes [`pe_eint_deb::W`](W) writer structure"]
106impl crate::Writable for PE_EINT_DEB_SPEC {
107    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
108    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
109}
110#[doc = "`reset()` method sets pe_eint_deb to value 0"]
111impl crate::Resettable for PE_EINT_DEB_SPEC {
112    const RESET_VALUE: Self::Ux = 0;
113}
d1_pac/gpio/pe_eint_deb.rs

d1_pac/gpio/
pe_eint_deb.rs
